A CMOS current-mode S-shape correction circuit with shape-adjustable control is proposed for suiting different LCD panel's characteristics from different manufactures. The correction shape is divided into three segments for easy curve-fitting using three lower order polynomials. Each segment could be realized by a corresponding current-mode circuit. The proposed circuit consists of several control points which are designed for tuning the correction shape. The S-shape correction circuit was fabricated using the 0.35 µm TSMC CMOS technology. The measured input dynamic range of the circuit is from 0 µA to 220 µA. The -3 dB bandwidth of the circuit is up to 262 MHz in a high input current region.

Reverse-recovery modeling for p-i-n diodes in the high current-density conditions are discussed. With the dynamic carrier-distribution-based modeling approach, the reverse recovery behaviors are explained in the high current-density conditions, where the nonquasi-static (NQS) behavior of carriers in the drift region is considered. In addition, a specific feature under the high current-density condition is discussed. The proposed model is implemented into a commercial circuit simulator in the Verilog-A language and its reverse recovery modeling ability is verified with a two-dimensional (2D) device simulator, in comparison to the conventional lumped-charge modeling technique.

This paper proposes an easy-to-design, theory-consistent compact feeding circuit, with a single input and four outputs, being comprised of two hybrid circuits that are capable of switching a beam in three directions. The circuits that determine the phase differences between the antennas are present on the same single layer, and thus there is no effect of vias and the design agrees well with the underlying theory. In addition, the vertically and horizontally symmetrical circuit pattern contributes to a substantial reduction in design time. The circuit is designed for use in the ISM band and its properties are evaluated using an RF circuit simulator. A prototype is fabricated and evaluated. The results of the simulation and measurement agree well with the theoretical values. The dimensions of the feeding circuit are 75 (H)55 (W)3.0 (T) mm.

We propose a novel dynamic hierarchical optical path network architecture that achieves efficient optical fast circuit switching. In order to complete wavelength path setup/teardown efficiently, the proposed network adaptively manages waveband paths and bundles of optical paths, which provide virtual mesh connectivity between node pairs for wavelength paths. Numerical experiments show that operational and facility costs are significantly reduced by employing the adaptive virtual waveband connections.

Based on a reverse converter algorithm derived from the New Chinese Remainder Theorem I, an algorithm for sign detection of RNS {2n-1, 2n, 2n+1} is presented in this paper. The hardware of proposed algorithm can be implemented using two n-bit additions and one (n+1)-bit comparator. Comparing with the previous paper, the proposed algorithm has reduced the number of additions used in the circuit. The experimental results show that the proposed circuit achieves 17.3% savings in area for small moduli and 10.5% savings in area for large moduli on an average, with almost the same speed. The power dissipations obtain 12.6% savings in average.

This paper presents a response time acceleration technique in a high-gain capacitive-feedback frontend amplifier (FA) for high output impedance sensors. Using an auxiliary amplifier as a unity-gain buffer, a sample-and-hold capacitor which is used for band-limiting and sampling the FA output is driven at the beginning of the transient response to make the response faster and then it is re-charged directly by the FA output. A condition and parameters for the response time acceleration using this technique while maintaining the noise level unaffected are discussed. Theoretical analysis and simulation results show that the response time can be less than half of the case without the acceleration technique for the specified settling error of less than 0.5%.

This paper presents a novel CMOS readout circuit for satellite infrared time delay and integration (TDI) arrays. An integrate-while-read method is adopted, and a dead-pixel-elimination circuit for solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is proposed to improve the signal-to-noise ratio (SNR) for low-temperature targets. The readout circuit was fabricated with a 0.35-µm CMOS process for a 5004 mid-wavelength infrared (MWIR) HgCdTe detector array. Using the circuit, a 90% background-limited infrared photodetection (BLIP) is satisfied over a wide input range (∼200–330 K), and the SNR is improved by 11 dB for the target temperature of 200 K.

This paper clarifies the bifurcation structure of the chaotic attractor in an interrupted circuit with switching delay from theoretical and experimental view points. First, we introduce the circuit model and its dynamics. Next, we define the return map in order to investigate the bifurcation structure of the chaotic attractor. Finally, we discuss the dynamical effect of switching delay in the existence region of the chaotic attractor compared with that of a circuit with ideal switching.

A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

A generalized version of sequential logic circuit based neuron models is presented, where the dynamics of the model is modeled by an asynchronous cellular automaton. Thanks to the generalizations in this paper, the model can exhibit various neuron-like waveforms of the membrane potential in response to excitatory and inhibitory stimulus. Also, the model can reproduce four groups of biological and model neurons, which are classified based on existence of bistability and subthreshold oscillations, as well as their underlying bifurcations mechanisms.

Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

400 V DC power distribution systems for data centers require a fast response DC circuit breaker is required. The semiconductor DC circuit breaker is an important key technology in DC power distribution systems. This paper considers the malfunction of Silicon Carbide- Static Induction Transistor (SiC-SIT) based DC circuit breakers in 400 V DC power distribution systems for data centers. The malfunction mechanism is explained, and a solution is proposed. Investigations are achieved by MATLAB/Simulink and experimental verification.

This paper proposes a write resistance tracking circuit (WRTC) to improve the memory window of HfOx-based resistive memory. With a 50-ns single voltage pulse, the minimal resistance of the high resistance state in the 1-kb array of resistive switching elements can increase from 25 kΩ to 65 kΩ by using the proposed verify circuit. The WRTC uses the transition current detection method based on the feedback of the memory cell to control the write driver. The WRTC achieves distinct bistable resistance states, avoids the occurrence of over-RESET, and enhances the memory window of the RRAM cell.

We have developed a long-range asynchronous on-chip data-transmission link based on multiple-valued single-track signaling for a highly reliable asynchronous Network-on-Chip. In the proposed signaling, 1-bit data with control information is represented by using a one-digit multi-level signal, so serial data can be transmitted asynchronously using only a single wire. The small number of wires alleviates the routing complexity of wiring long-range interconnects. The use of current-mode signaling makes it possible to transmit data at high speed without buffers or repeaters over a long interconnect wire because of the low-voltage swing of signaling, and it leads to low-latency data transmission. We achieve a latency of 0.45 ns, a throughput of 1.25 Gbps, and energy dissipation of 0.58 pJ/bit with a 10-mm interconnect wire under a 0.13 µm CMOS technology. This represents an 85% decrease in latency, a 150% increase in throughput, and a 90% decrease in energy dissipation compared to a conventional serial asynchronous data-transmission link.

A low-power switching method using a bootstrapping circuit is proposed for a high-speed output driver of transmitter. Compared with a conventional output driver, the proposed scheme employs only nMOSFETs to transmit data. The bootstrapping circuit ensures the proper switching of nMOSFET. The proposed scheme is simulated and fabricated using a 0.18 µm CMOS technology, showing 10.2% lower power consumption than a conventional switching driver at 2.5 Gb/s data rate.

In this paper, we designed and fabricated large scale micro-light-emitting-diode (LED) arrays and silicon driver for single chip device for realizing as prototypes of heterogeneous optoelectronic integrated circuits (OEICs). The large scale micro-LED arrays were separated by a dry etching method from mesa structure to 16,384 pixels of 128 128, each with a size of 15 µm in radius. Silicon driver was designed the additional bonding pad on each driving transistor for bonding with micro-LED arrays. Fabricated micro-LED arrays and driver were flip-chip bonded using anisotropic conductive adhesive.

In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation. The proposed method iteratively applies behavioral synthesis and floorplanning to obtain a near optimum circuit in the term of latency under given design constraints. To improve latency, behavioral synthesis and floorplanning are carried out so that the delay of the control circuit is minimized and the addition of delay elements to satisfy timing constraints is minimized. We evaluate the effectiveness of the proposed method in terms of latency, area, and the number of timing violations while synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to the circuit synthesized without the proposed method. Also, the proposed method is effective to reduce the number of timing violations.

As process technology is scaled down, a typical system on a chip (SoC) becomes denser. In scaled process technology, process variation becomes greater and increasingly affects the SoC circuits. Moreover, the process variation strongly affects network-on-chips (NoCs) that have a synchronous network across the chip. Therefore, its network frequency is degraded. We propose a process-variation-adaptive NoC with a variation-adaptive variable-cycle router (VAVCR). The proposed VAVCR can configure its cycle latency adaptively on a processor core basis, corresponding to the process variation. It can increase the network frequency, which is limited by the process variation in a conventional router. Furthermore, we propose a variable-cycle pipeline adaptive routing (VCPAR) method with VAVCR; the proposed VCPAR can reduce packet latency and has tolerance to network congestion. The total execution time reduction of the proposed VAVCR with VCPAR is 15.7%, on average, for five task graphs.