IEICE TRANSACTIONS on Electronics
InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate
Summary :
We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E95-C No.8 pp.1369-1375
- Publication Date
- 2012/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E95.C.1369
- Type of Manuscript
- Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2011)
- Category
- Emerging Devices
Authors
Kai BLEKKER
Rene RICHTER
Ryosuke ODA
Satoshi TANIYAMA
Oliver BENNER
Gregor KELLER
Benjamin MUNSTERMANN
Andrey LYSOV
Ingo REGOLIN
Takao WAHO
Werner PROST
Keyword
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Kai BLEKKER, Rene RICHTER, Ryosuke ODA, Satoshi TANIYAMA, Oliver BENNER, Gregor KELLER, Benjamin MUNSTERMANN, Andrey LYSOV, Ingo REGOLIN, Takao WAHO, Werner PROST, "InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 8, pp. 1369-1375, August 2012, doi: 10.1587/transele.E95.C.1369.
Abstract: We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1369/_p
Copy
@ARTICLE{e95-c_8_1369,
author={Kai BLEKKER, Rene RICHTER, Ryosuke ODA, Satoshi TANIYAMA, Oliver BENNER, Gregor KELLER, Benjamin MUNSTERMANN, Andrey LYSOV, Ingo REGOLIN, Takao WAHO, Werner PROST, },
journal={IEICE TRANSACTIONS on Electronics},
title={InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate},
year={2012},
volume={E95-C},
number={8},
pages={1369-1375},
abstract={We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.},
keywords={},
doi={10.1587/transele.E95.C.1369},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - InAs Nanowire Circuits Fabricated by Field-Assisted Self-Assembly on a Host Substrate
T2 - IEICE TRANSACTIONS on Electronics
SP - 1369
EP - 1375
AU - Kai BLEKKER
AU - Rene RICHTER
AU - Ryosuke ODA
AU - Satoshi TANIYAMA
AU - Oliver BENNER
AU - Gregor KELLER
AU - Benjamin MUNSTERMANN
AU - Andrey LYSOV
AU - Ingo REGOLIN
AU - Takao WAHO
AU - Werner PROST
PY - 2012
DO - 10.1587/transele.E95.C.1369
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2012
AB - We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.
ER -
English
