A unipolar n-n heterostrucuture diode is developed in the InP material system. The electronic barrier is formed by a saw tooth type of conduction band bending which consists of a quaternary In0.52(AlyGa1-y)0.48As layer with 0 < y < ymax. This barrier is lattice matched for all y to InP and is embedded between two n+-InGaAs layers. By varying the maximum Al-content from ymax,1 = 0.7 to ymax,2 = 1 a variable barrier height is formed which enables a diode-type I-V characteristic by epitaxial design with an adjustable current density within 3 orders of magnitude. The high current density of the diode with the lower barrier height (ymax,1 = 0.7) makes it suitable for high frequency applications at low signal levels. RF measurements reveal a speed index of 52 ps/V at VD = 0.15 V. The device is investigated for RF-to-DC power conversion in UHF RFID transponders with low-amplitude RF signals.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.