Ultrahigh-speed compact flash analog-to-digital converters (ADCs) using resonant-tunneling diodes (RTDs) have been designed to demonstrate a high potential of RTD circuits. Novel multi-input subtraction gates are introduced to the encoder to obtain a compact circuit configuration. By assuming 0.1-µm InP-based RTD/HEMT technology, circuit simulations of 4-bit 10-GHz flash ADCs are carried out. It is found that the device counts of the ADC with an 8-input gate are one third that of the ADC with 4-input gates. This leads to a reduction in the power dissipation by 50%. In addition, bandwidths of more than 20 GHz have been obtained for 4-bit and 5-bit ADCs at a sampling frequency of 10 GHz.

A switched-capacitor integrator based on dynamic source follower amplifiers has been proposed. Integrator operation has been confirmed and analyzed by assuming 0.18-µm CMOS technology. The integrator can reduce the number of elements considerably compared with conventional ones using operational amplifiers. As a result, the power dissipation of proposed integrator can be reduced to approximately one-eighth that of conventional integrators. The integrator is applied to a second-order ΔΣ modulator, and its successful operation has been confirmed by transistor-level circuit simulation.

A feedforward (FF) network using ΔΣ modulators is investigated to implement a non-binary analog-to-digital (A/D) converter. Weighting coefficients in the network are determined to suppress the generation of quantization noise. A moving average is adopted to prevent the analog signal amplitude from increasing beyond the allowable input range of the modulators. The noise transfer function is derived and used to estimate the signal-to-noise ratio (SNR). The FF network output is a non-uniformly distributed multi-level signal, which results in a better SNR than a uniformly distributed one. Also, the effect of the characteristic mismatch in analog components on the SNR is analyzed. Our behavioral simulations show that the SNR is improved by more than 30 dB, or equivalently a bit resolution of 5 bits, compared with a conventional first-order ΔΣ modulator.

HEMT comparators for ultrahigh-speed A/D converters have been investigated. In particular, the transition times of the D-latch used in the comparator have been analyzed by assuming a 0.1-µm HEMT technology. It is found that for small input signals (<0.1 V), the transition time from the track to latch phase dominates the comparator operation speed. As the input signal increases, this time decreases due to the positive feedback in the latch, and the comparator speed is limited by the transition time from the latch to track phase. The transition times of 20 ps have been estimated for the present comparator.

Ultrahigh-speed continuous-tine delta-sigma modulators (DSMs) have been designed by using a fully-differential comparator consisting of resonant-tunneling diodes (RTDs) and HEMTs. Continuous-time lowpass and bandpass filters using HEMTs have also been incorporated to obtain lowpass- and bandpass-type DSMs, respectively. Circuit simulation assuming 0.1-µm InP-based HEMT and RTD technology has revealed a successful operation of the 2nd-order lowpass DSM at a sampling frequency of 20 GHz. The clock frequency was 10 GHz because of the double sampling function of the present comparator. The 2nd-order bandpass DSM has also been designed with a center frequency of 3 GHz. These results clearly show high potential of the present delta-sigma modulators.

A flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates is proposed. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued multiple-input monostable-bistable transition logic element (M2-MOBILE). By assuming InP-based resonant-tunneling diode (RTD) and heterojunction field-effect transistor technology, we have carried out SPICE simulation that demonstrates a 4-bit, 10-GS/s ADC operation. The input bandwidth, defined as a frequency at which the effective number of bit decreases by 0.5 LSB, was also estimated to be 500 MHz. Compact circuit configuration, which is due to the combination of MML and M2-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.

Improvement in circuit performance of Josephson logic devices is described and discussed. A high sensitivity switching gate of asymmetrical two junction interferometer is proposed, in which the Josephson threshold current of the junctions is unequal to each other but the bias feeding point is selected so as to balance inductance threshold current product on the left and the right hand side branch. Transmission lines with characteristic impedance as high as 4Ω were realized on a new superconducting ground plane structure with SiO2 overlying insulation. High resistivity resistor material of gold-indium alloy was also developed for resistive termination. A series-connected 4 stage OR gate chain was experimentally constructed with the present switching gates, transmission lines, and termination resistors. The circuit performance measurements demonstrated that the average speed power product was as small as 0.9 fJ per single stage.

Based on the similarity in current-voltage characteristics of resonant-tunneling diodes (RTDs) and tunneling-type superconductive Josephson junctions, novel current-mode logic circuits consisting of four RTDs have been proposed. NAND and NOR functions, as well as AND and OR, can be obtained in a simple circuit configuration. SPICE simulation showed that the present circuits can operate at a clock frequency as high as 200 GHz.

This paper presents the device technology for monolithic integration of InP-based resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs). The potential of this technology for applications in quantum functional devices and circuits is demonstrated in two integration schemes in which RTDs and FETs are integrated either in Parallel or in series. Based on the parallel integration scheme, we demonstrate an integrated device which exhibits negative differential resistance and modulated peak current. This integrated device forms the foundation of a new category of functional circuits featuring clocked supply voltage. Based on the series integration scheme, resonant-tunneling high electron mobility transistors (RTHEMTs) with novel current-voltage characteristics and useful circuit applications are demonstrated. The high-frequency characteristics of RTHEMTs are also reported.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

We study ultrafast operation of multiple-valued quantizers composed of resonant-tunneling diodes (RTDs) and high electron mobility transistors (HEMTs). The operation principle of these quantizers is based on the monostable-multistable transition logic (MML) of series-connected RTDs. The quantizers are fabricated by monolithically integrating InP-based RTDs and 0.7-µm-gate-length HEMTs with a cutoff frequency of 40 GHz. To perform high-frequency experiments, an output buffer and termination resistors are attached to the quantizers, and the quantizers are designed to accommodate high-frequency input signals. Our experiments show that both ternary and quaternary quantizers can operate at clock frequencies of 10 GHz and at input frequencies of 3 GHz. This demonstrates the potential of applying RTD-based multiple-valued quantizers to high-frequency circuits.

An energy-efficient ΔΣ modulator using a novel switched-capacitor-based integrator has been investigated. The proposed dynamic integrator uses a common-source configuration, where a MOSFET turns off after the charge redistribution is completed. Thus, only the subthreshold current flows through the integrator, resulting in high energy efficiency. A constant threshold voltage works as the virtual ground in conventional opamp-based integrators. The performance has been estimated for a 2nd-order ΔΣ modulator by transistor-level circuit simulation assuming a 0.18-µm standard CMOS technology. An FOM of 29fJ/conv-step was obtained with a peak SNDR of 82.6dB for a bandwidth and a sampling frequency of 20kHz and 5MHz, respectively.