We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

A searchable symmetric encryption (SSE) scheme is a method that searches encrypted data without decrypting it. In this paper, we address the substring search problem such that for a set D of documents and a pattern p, we find all occurrences of p in D. Here, a document and a pattern are defined as a string. A directed acyclic word graph (DAWG), which is a deterministic finite automaton, is known for solving a substring search problem on a plaintext. We improve a DAWG so that all transitions of a DAWG have distinct symbols. Besides, we present a space-efficient and secure substring SSE scheme using an improved DAWG. The proposed substring SSE scheme consists of an index with a simple structure, and the size is O(n) for the total size n of documents.