We have developed the flexible dual-gate OFET based pressure sensor using a thin polyethylene naphthalate (PEN, 25 µm) film as a substrate. The performance was equivalent to that fabricated on the glass substrate, and it could also be used on the curved surface. Drain current in the flexible pressure sensor was increased according to the pressure load without application of gate voltage. The magnitude of the change in drain current with respect to pressure application was about 2.5 times larger than that for the device on the glass substrate.

We integrate a pressure sensing capacitor and a low operation voltage OFET to develop a pressure sensor. The OFET was used as a readout device and an external pressure was loaded on the sensing capacitor. The OFET operates at less than 5 V and the change in the drain current in response to the pressure load (100 kPa) is two orders of magnitude.

We deposited thin films of thiophene/phenylene co-oligomers (TPCOs) onto poly(tetrafluoroethylene) (PTFE) layers that were friction-transferred on substrates. These films were composed of aligned molecules in such a way that their polarizations of emissions and absorbances were larger along the drawing direction than those perpendicular to that direction. Organic field-effect transistors (OFETs) fabricated with these films indicated large mobilities, when the drawing direction of PTFE was parallel to the channel length direction. The friction-transfer technique forms the TPCO films that indicate the anisotropic optical and electronic properties.

Step-edge vertical channel organic field-effect transistors (SVC-OFETs) with a very short channel have been fabricated by a novel selective electrospray deposition (SESD) method. We propose the SESD method for the fabrication of SVC-OFETs based on a 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-pentacene) semiconductor layer formed by SESD. In the SESD method, an electric field is applied between the nozzle and selective patterned electrodes on a substrate. We demonstrated that the solution accumulates on the selected electrode pattern by controlling the voltage applied to the electrode.

In this work, a gate-all-around (GAA) tunneling field-effect transistor (TFET) with InGaAs/Si heterojunction for high-performance and low-standby power operations is studied. Gallium (Ga) compositon ($x)$ in In$_{1-x}$Ga$_{x}$As source substantially affects the physical properties related with device performances including lattice constant, bandgap energy, effective tunneling mass, channel mobility, and others. Thus, it is worthy investigating the effect of Ga fraction on performances of the proposed heterojunction TFET. For this goal, the device design and its performance evaluation are carried out by technology computer-aided design (TCAD). Direct-current (DC) performances are investigated in terms of on-state current ($I_{ m{on}})$, off-state current ($I_{ m{off}})$, current ratio ($I_{ m{on}}$/$I_{ m{off}})$, and subthreshold swing ($S$). Furthermore, it is shown that the device with an n-type Si insertion layer between source and channel demonstrates the enhanced DC characteristics.

In this paper, we present the validity and potential capacity of a modeling and simulation environment for the nonresonant plasmonic terahertz (THz) detector based on the silicon (Si) field-effect transistor (FET) with a technology computer-aided design (TCAD) platform. The nonresonant and “overdamped” plasma-wave behaviors have been modeled by introducing a quasi-plasma electron charge box as a two-dimensional electron gas (2DEG) in the channel region only around the source side of Si FETs. Based on the coupled nonresonant plasma-wave physics and continuity equation on the TCAD platform, the alternate-current (AC) signal as an incoming THz wave radiation successfully induced a direct-current (DC) drain-to-source output voltage as a detection signal in a sub-THz frequency regime under the asymmetric boundary conditions with a external capacitance between the gate and drain. The average propagation length and density of a quasi-plasma have been confirmed as around 100 nm and 11019/cm3, respectively, through the transient simulation of Si FETs with the modulated 2DEG at 0.7 THz. We investigated the incoming radiation frequency dependencies on the characteristics of the plasmonic THz detector operating in sub-THz nonresonant regime by using the quasi-plasma modeling on TCAD platform. The simulated dependences of the photoresponse with quasi-plasma 2DEG modeling on the structural parameters such as gate length and dielectric thickness confirmed the operation principle of the nonresonant plasmonic THz detector in the Si FET structure. The proposed methodologies provide the physical design platform for developing novel plasmonic THz detectors operating in the nonresonant detection mode.

A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.

We have fabricated printed active antenna for flexible information tag which have a loop antenna combined with step-edge vertical channel organic field-effect transistor (SVC-OFET). Fabrication using printing process, characterization of SVC-OFETs, and performances of active antenna elements are discussed in detail.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control VT of the TFET by putting an additional VT-control doping region (VDR) between source and channel. We examine how much VT is changed by doping concentration of VDR. The change of doping concentration modulates VT because it changes the semiconductor work function difference, ψs,channel-ψs,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted VT of TFET is also investigated.

We have investigated the low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Based on the device-level comparison of HG, SiO2-only and high-k-only TFETs, their circuit performance and energy consumption have been discussed. It has been shown that HG TFETs can deliver 14400x higher performance than the SiO2-only TFETs and 17x higher performance than the high-k-only TFETs due to its higher on current and lower capacitance at the same static power, same power supply. It has been revealed that HG TFETs have better voltage scalability than the others. It is because HG TFETs dissipate only 8% of energy consumption of SiO2-only TFETs and 17% of that of high-k-only TFETs under the same performance condition.

Electrical performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) based on a silicon germanium (Si1-xGex) layer have been investigated in terms of subthreshold swing (SS), on/off current ratio, on-state current (Ion). Cut-off frequency (fT) and maximum oscillation frequency (fmax) were demonstrated from small-signal parameters such as effective gate resistance (Rg), gate-drain capacitance (Cgd), and transconductance (gm). According to the technology computer-aided design (TCAD) simulation results, the current drivability, fT, and fmax of GAA TFETs based on Si1-xGex layer were higher than those of GAA TFETs based on silicon. The simulated devices had 60 nm channel length and 10 nm channel radius. A GAA TFET with x = 0.4 had maximum Ion of 51.4 µA/µm, maximum fT of 72 GHz, and maximum fmax of 610 GHz. Additionally, improvements of performance at the presented device with PNPN junctions were demonstrated in terms of Ion, SS, fT, and fmax. When the device was designed with x = 0.4 and n+ layer width (Wn) = 6 nm, it shows Ion of 271 µA/µm, fT of 245 GHz, and fmax of 1.49 THz at an operating bias (VGS = VDS = 1.0 V).

Thin-film transistors based on Liquid-crystalline phenylterthiophenes, 3-TTPPh-5 and 3-TTPPhF4-6 are fabricated with a spin-coating method. The devices exhibit p-type operation with the mobility on the order of 10-2 cm2V-1s-1. The field-effect mobilities of the transistors using 3-TTPPh-5 and 3-TTPPhF4-6 are almost independent of the temperature above room temperature. In particular, the temperature range in which the mobility is constant is between 230 and 350 K for 3-TTPPh-5.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

Silicon Mach-Zehnder interferometric (MZI) waveguide modulator incorporating the n-channel junction field-effect transistor (JFET) as a signal modulation unit was designed, fabricated, and analyzed. The proposed MZI with JFET was designed to operate based on the plasma dispersion effect in the infrared wavelength of 1550 nm. The three different modulation lengths (ML) of 500, 1000, and 2000 µm while keeping the overall MZI length constant at 1.5 cm were set as a general design rule for these 10 µm-wide MZIs under study. When the JFET was operated in an active mode by injecting approximately 50 mA current (Is) to achieve a π phase shift, the modulation efficiency of the device was measured to be η = π /(Is· L) 40π/A-mm. The temporal and frequency response measurements also demonstrate that the respectively rise and fall times measured using a high-speed photoreceiver were in the neighborhood of 8.5 and 7.5 µsec and the 3 dB roll-off frequency (f3 dB) measured was in the excess of 400 kHz.

We have investigated the effect of deoxyribonucleic acid (DNA) adsorption on a graphene field-effect-transistor (FET) device. We have used graphene which is grown on a Ni substrate by chemical vapour deposition. The Raman spectra of our graphene indicate its high quality, and also show that it consists of only a few layers. The current-voltage characteristics of our bare graphene strip FET show a hole conduction behavior, and the gate sensitivity of 0.0034 µA/V, which is reasonable with the size of the strip (510 µm2). After the adsorption of 30 base pairs single-stranded poly (dT) DNA molecules, the conductance and gate operation of the graphene FET exhibit almost 11% and 18% decrease from those of the bare graphene FET device. The observed change may suggest a large sensitivity for a small enough (nm size) graphene strip with larger semiconducting property.

We propose a gate-all-around tunnel field effect transistor (GAA TFET) having a n-doped layer at the source junction and investigate its electrical characteristics with device simulation. By introducing the n-doped layer, band-to-band tunneling area is increased and tunneling barrier width is decreased. Also, electric field induced by gate bias is increased by the surrounding gate structure, which makes it possible to obtain a more abrupt band-bending. These effects bring about a significant improvement in on-current and subthreshold characteristics. GAA TFET with n-doped layer shows subthreshold swing at Id = 1 nA/µm of 32.5 mV/dec, average subthreshold swing of 20.6 mV/dec. With comparison to other TFET structures, the merits of the proposed device are demonstrated and performance dependences on device parameters are characterized by extensive simulations.

The control of the organic field-effect transistor characteristics is necessary to produce the integrated circuits using organic semiconductors. Variations in the poly (3-hexylthiophene) field-effect transistor characteristics upon post-treatment such as thermal treatment and voltage treatment in N2 atmosphere have been investigated. The controllability and reproducibility of the threshold voltage and mobility were achieved as a result of the post-treatments.

Time-resolved microscopic optical second harmonic generation (TRM-SHG) imaging measurement revealed quantitatively the potential drop at the electrode contact of pentacene field effect transistors (FET). An activation of the SH signal at the edge of Ag-source electrode indicates the presence of large potential drop at pentacene-Ag contact during device operation, whereas negligible potential drop was observed at pentacene-Au contact. These findings agree with the injection characteristics of electrodes owing to the relationship between the work function of the metal and the HOMO level of pentacene.

In many different bioelectronic applications silicon field-effect devices such as transistors or nanowires are used. Usually native or thermally grown silicon oxides serve as interfacing layer to the liquid. For an effective voltage to current conversion of the devices, the main demands for interface layers are low leakage current, low defect density, and high input capacitance. In this article we describe the fabrication and characterization of ultra-thin silicon oxide/high-κ material stacks for bioelectronics. A combination of ultra-thin silicon oxide and DyScO3 revealed the best results. This material stack is particularly interesting for future fabrication of field-effect devices for bioelectronic applications.