Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer
Summary :
A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.5 pp.644-648
- Publication Date
- 2013/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.644
- Type of Manuscript
- Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jae Hwa SEO, Jae Sung LEE, Yun Soo PARK, Jung-Hee LEE, In Man KANG, "Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 5, pp. 644-648, May 2013, doi: 10.1587/transele.E96.C.644.
Abstract: A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.644/_p
Copy
@ARTICLE{e96-c_5_644,
author={Jae Hwa SEO, Jae Sung LEE, Yun Soo PARK, Jung-Hee LEE, In Man KANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer},
year={2013},
volume={E96-C},
number={5},
pages={644-648},
abstract={A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.},
keywords={},
doi={10.1587/transele.E96.C.644},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer
T2 - IEICE TRANSACTIONS on Electronics
SP - 644
EP - 648
AU - Jae Hwa SEO
AU - Jae Sung LEE
AU - Yun Soo PARK
AU - Jung-Hee LEE
AU - In Man KANG
PY - 2013
DO - 10.1587/transele.E96.C.644
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2013
AB - A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.
ER -
English
