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[Keyword] tunneling field-effect transistor (TFET)(4hit)

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  • InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

    Sung YUN WOO  Young JUN YOON  Jae HWA SEO  Gwan MIN YOO  Seongjae CHO  In MAN KANG  

     
    PAPER

      Vol:
    E97-C No:7
      Page(s):
    677-682

    In this work, a gate-all-around (GAA) tunneling field-effect transistor (TFET) with InGaAs/Si heterojunction for high-performance and low-standby power operations is studied. Gallium (Ga) compositon ($x)$ in In$_{1-x}$Ga$_{x}$As source substantially affects the physical properties related with device performances including lattice constant, bandgap energy, effective tunneling mass, channel mobility, and others. Thus, it is worthy investigating the effect of Ga fraction on performances of the proposed heterojunction TFET. For this goal, the device design and its performance evaluation are carried out by technology computer-aided design (TCAD). Direct-current (DC) performances are investigated in terms of on-state current ($I_{ m{on}})$, off-state current ($I_{ m{off}})$, current ratio ($I_{ m{on}}$/$I_{ m{off}})$, and subthreshold swing ($S$). Furthermore, it is shown that the device with an n-type Si insertion layer between source and channel demonstrates the enhanced DC characteristics.

  • Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer

    Jae Hwa SEO  Jae Sung LEE  Yun Soo PARK  Jung-Hee LEE  In Man KANG  

     
    PAPER

      Vol:
    E96-C No:5
      Page(s):
    644-648

    A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off-current (Ion and Ioff), subthreshold swing (SS), and RF performances.

  • Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)

    Gibong LEE  Woo Young CHOI  

     
    BRIEF PAPER

      Vol:
    E95-C No:5
      Page(s):
    910-913

    We have investigated the low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Based on the device-level comparison of HG, SiO2-only and high-k-only TFETs, their circuit performance and energy consumption have been discussed. It has been shown that HG TFETs can deliver 14400x higher performance than the SiO2-only TFETs and 17x higher performance than the high-k-only TFETs due to its higher on current and lower capacitance at the same static power, same power supply. It has been revealed that HG TFETs have better voltage scalability than the others. It is because HG TFETs dissipate only 8% of energy consumption of SiO2-only TFETs and 17% of that of high-k-only TFETs under the same performance condition.

  • Performance of Gate-All-Around Tunneling Field-Effect Transistors Based on Si1-x Gex Layer

    Jae Sung LEE  In Man KANG  

     
    PAPER

      Vol:
    E95-C No:5
      Page(s):
    814-819

    Electrical performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) based on a silicon germanium (Si1-xGex) layer have been investigated in terms of subthreshold swing (SS), on/off current ratio, on-state current (Ion). Cut-off frequency (fT) and maximum oscillation frequency (fmax) were demonstrated from small-signal parameters such as effective gate resistance (Rg), gate-drain capacitance (Cgd), and transconductance (gm). According to the technology computer-aided design (TCAD) simulation results, the current drivability, fT, and fmax of GAA TFETs based on Si1-xGex layer were higher than those of GAA TFETs based on silicon. The simulated devices had 60 nm channel length and 10 nm channel radius. A GAA TFET with x = 0.4 had maximum Ion of 51.4 µA/µm, maximum fT of 72 GHz, and maximum fmax of 610 GHz. Additionally, improvements of performance at the presented device with PNPN junctions were demonstrated in terms of Ion, SS, fT, and fmax. When the device was designed with x = 0.4 and n+ layer width (Wn) = 6 nm, it shows Ion of 271 µA/µm, fT of 245 GHz, and fmax of 1.49 THz at an operating bias (VGS = VDS = 1.0 V).