In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation. The proposed method iteratively applies behavioral synthesis and floorplanning to obtain a near optimum circuit in the term of latency under given design constraints. To improve latency, behavioral synthesis and floorplanning are carried out so that the delay of the control circuit is minimized and the addition of delay elements to satisfy timing constraints is minimized. We evaluate the effectiveness of the proposed method in terms of latency, area, and the number of timing violations while synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to the circuit synthesized without the proposed method. Also, the proposed method is effective to reduce the number of timing violations.

This paper presents recent progress made in the development of an optical packet and circuit integrated network. From the viewpoint of end users, this is a single network that provides both high-speed, inexpensive services and deterministic-delay, low-data-loss services according to the users' usage scenario. From the viewpoint of network service providers, this network provides large switching capacity with low energy requirements, high flexibility, and efficient resource utilization with a simple control mechanism. The network we describe here will contribute to diversification of services, enhanced functional flexibility, and efficient energy consumption, which are included in the twelve design goals of Future Networks announced by ITU-T (International Telecommunication Union - Telecommunication Standardization Sector). We examine the waveband-based network architecture of the optical packet and circuit integrated network. Use of multi-wavelength optical packet increases the switch throughput while minimizing energy consumption. A rank accounting method provides a solution to the problem of inter-domain signaling for end-to-end lightpath establishment. Moving boundary control for packet and circuit services makes for efficient resource utilization. We also describe related advanced technologies such as waveband switching, elastic lightpaths, automatic locator numbering assignment, and biologically-inspired control of optical integrated network.

To realize economical optical burst signal receivers for the Optical Network Unit (ONU) of the Ethernet Optical Switched Access Network (E-OSAN), we previously implemented optical burst receivers with AC-coupling and DC-coupling using off-the-shelf components, and showed that the former offers better performance. This paper proposes a new optical burst signal receiver that uses the transfer function, Gn(s) = 1-Hn(s), where Hn(s) denotes a Bessel filter transfer function of order n. We also present a method for designing the proposed receiver and clarify that it has better performance than the conventional AC-coupling one. We then present an LCR circuit synthesis of Gn(s), which is necessary to actually implement a burst receiver based on the proposal.

A novel type of optically clocked all-optical flip-flop based on a coupled-mode distributed Bragg reflector laser diode is proposed. The device operates as a bistable laser, where the two lasing modes at different wavelength are switched all-optically by injecting a clock pulse together with a set/reset signal. We employ an analytical model based on the two-mode coupled rate equations to verify the basic operation of the device numerically. Optically clocked flip-flop operation is obtained with a set/reset power of 0.60 mW and clock power of 1.8 mW. The device features simple structure, small footprint, and synchronized all-optical flip-flop operation, which should be attractive in the future digital photonic integrated circuits.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

A technique to reduce noise transfer functions (NTF) of switched-capacitor (SC) integrators without changing their signal transfer functions (STF) is proposed. The proposed technique based on a simple reconnection scheme of multiple sampling capacitors. It can be implemented into any SC integrators as long as they have a transfer delay. A design strategy is also given to reduce the effect of parasitic capacitors. An SC integrator with a small total capacitance and a low noise transfer gain based on the proposed technique is also proposed. For a given design example, the total capacitance and the simulated noise transfer gain of the proposed SC integrator are 37% and 90% less than the conventional one.

True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64–256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.

A new sustain driving circuit, featuring an energy-recovering function with simple structure and minimal component count, is proposed as a cost-effective solution for driving plasma display panels during the sustaining period. Compared with existing solutions, the proposed circuit reduces the number of semiconductor switches and reactive circuit components without compromising the circuit performance and gas-discharging characteristics. In addition, the proposed circuit utilizes the harness wire as an inductive circuit component, thereby further simplifying the circuit structure. The performance of the proposed circuit is confirmed with a 42-inch plasma display panel.

Substrate noise coupling has been seriously concerned in the design of advanced analog and radio frequency (RF) integrated circuits (ICs). This paper reviews recent advancements in the modeling, analysis, and evaluation of substrate noise coupling at IC chip level. Noise generation from digital circuits and propagation to the area of analog circuits are clearly visualized both by full-chip simulation as well as by on-chip measurements, for silicon test vehicles. The impacts of substrate noise coupling are also in-depth discussed at device, circuit, as well as system levels. Overall understanding of substrate noise coupling will then provide the basics for highly reliable design of analog and RF ICs.

Physical channels of the intra-body communications, in which communications are performed by exciting electric field around the human body, have been treated as a capacitive circuit from the beginning of the development. Although the circuit-like understanding of the channels are helpful to design devices and systems, there is a problem that the results may be invalid if the circuit parameters are incorrectly estimated. In the present study, the values of the circuit parameters are properly derived by solving a boundary value problem of electric potentials of the conductors. Furthermore, approximate models which are appropriate for cases that some of the conductors are grounded are investigated.

This paper presents a 65-nm CMOS 8-antenna array transmitter operating in 117–130-GHz range for short range and portable millimeter-wave (mm-wave) active imaging applications. Each antenna element is a new on-chip antenna located on the top metal. By using on-chip transformer, pulse output of each resistor-less mm-wave pulse generators (PG) are sent to each integrated antenna. To adjust pulse delays for the purpose of pulse beam-forming, a 7-bit digitally programmable delay circuit (DPDC) is added to each of PGs. Moreover, in order to dynamically adjust pulse delays among eight SW's outputs, we implemented on-chip jitter and relative skew measuring circuit with 20-bit digital output to achieve cumulative distribution (CDF) and probability density (PDF) functions from which DPDC's input codes are decided to align eight antenna's output pulses. Two measured radiation peaks after relative skew alignment are obtained at (θ; φ) angles of (-56; 0) and (+57; 0). Measurement results shows that beam-forming angles of the fully integrated antenna array can be adjusted by digital input codes and by the on-chip skew adjustment circuit for active imaging applications.

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for 2-dimensional microbolometer infrared focal plane arrays (IRFPAs). The integration time and signal-to-noise ratio (SNR) is improved using the current-mode bias and MSB skimming. The proposed pixel-level ADC is a two-step configuration, so its power consumption is very low. The readout circuit was designed using a 0.35 µm 2-poly 4-metal CMOS process for a 320240 microbolometer array with a pixel size of 35µm35µm. The noise equivalent temperature difference (NETD) was estimated to be 47 mK, with a power consumption of 390 nW for a pixel-level ADC.

With the progress of process technology in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the on-chip decoupling capacitance optimization that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the on-chip decoupling capacitance area will reduce the chip area and, therefore, manufacturing costs. Hence, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the total on-chip decoupling capacitance area. The proposed algorithm uses the idea of the network algorithm where the path which has the most influence on voltage drop is found. Voltage drop is improved by adding the on-chip capacitance to the node on the path. The proposed algorithm is efficient and effectively adds the on-chip capacitance to the greatest influence on the voltage drop. Experimental results demonstrate that, with the proposed algorithm, real size power/ground network could be optimized in just a few minutes which are quite practical. Compared with the conventional algorithm, we confirmed that the total on-chip decoupling capacitance area of the power/ground network was reducible by about 4050%.

In recent Printed Circuit Boards (PCB), the design size and density have increased, and the improvement of routing tools for PCB is required. There are several routing tools which generate high quality routing patterns when connection requirement can be realized by horizontal and vertical segments only. However, in high density PCB, the connection requirements cannot be realized when only horizontal and vertical segments are used. Up to one third nets can not be realized if no non-orthogonal segments are used. In this paper, a routing method for a single-layer routing area that handles higher density designs in which 45-degree segments are used locally to relax the routing density is introduced. In the proposed method, critical zones in which non-orthogonal segments are required in order to realize the connection requirements are extracted, and 45-degree segments are used only in these zones. By extracting minimal critical zones, the other area that can be used to improve the quality of routing pattern without worry about connectivity issues is maximized. Our proposed method can utilize the routing methods which generate high quality routing pattern even if they only handle horizontal and vertical segments as subroutines. Experiments show that the proposed method analyzes a routing problem properly, and that the routing is realized by using 45-degree segments effectively.

The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

Integration of optical paths and packets in a switch is a key technique to support ultra-high-speed traffic in the future Internet. However, the question of how to efficiently allocate wavelengths for optical paths and optical packets has not been solved yet due to the lack of a systematic model to evaluate the performance of the integrated switch. In this paper, we model the operation of the integrated switch as a system of two queuing models: M/M/x/x for optical paths and M/M/1/LPS for optical packets. From the model, we find an optimal policy to dynamically allocate wavelength resources in an integrated switch. Simulation results demonstrate that our mechanism achieves better performance than other methods.

We propose a data transmission method for resonant wireless power transmission systems. In order to transmit data, we use the coils originally designed for power transmission, no additional antennas are required. We focus on uplink data transmission and adopt the load modulation technique. This configuration yields mid-range data transmission without transmitting power. In addition, the proposal enables simultaneous power feeding and uplink data transmission. We make a prototype demonstrating resonant wireless power transmission and measure its S-parameter under some load conditions. The results confirm the potential of load modulation in supporting uplink data transmission. Additionally, the results are elucidated by analyzing an equivalent circuit. Measured S-parameter and equivalent circuit response are found to be similar.

An asynchronous sequential logic spiking neuron is an artificial neuron model that can exhibit various bifurcations and nonlinear responses to stimulation inputs. In this paper, a pulse-coupled system of the asynchronous sequential logic spiking neurons is presented. Numerical simulations show that the coupled system can exhibit various lockings and related nonlinear responses. Then, theoretical sufficient parameter conditions for existence of typical lockings are provided. Usefulness of the parameter conditions is validated by comparing with the numerical simulation results as well as field programmable gate array experiment results.

This study formulates and solves the wire planning problem with electro-migration and interference using an effective integer linear programming (ILP)-based approach. For circuits without obstacles, the proposed approach obtains a wire planning with the minimum wiring area. An effective approach for estimating the length of feasible routing wire is proposed to handle circuits with obstacles. In addition, the space reservation technique, which allocates the ring of the free silicon space around obstacles, is presented to improve interference among routing wires and on-obstacle wires. For circuits with obstacles, the proposed method minimizes total wiring area and reduces interference. Experimental results show that the integer linear-programming-based approach effectively and efficiently minimizes wiring area of routing wires.

A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.