The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for 2-dimensional microbolometer infrared focal plane arrays (IRFPAs). The integration time and signal-to-noise ratio (SNR) is improved using the current-mode bias and MSB skimming. The proposed pixel-level ADC is a two-step configuration, so its power consumption is very low. The readout circuit was designed using a 0.35 µm 2-poly 4-metal CMOS process for a 320240 microbolometer array with a pixel size of 35µm35µm. The noise equivalent temperature difference (NETD) was estimated to be 47 mK, with a power consumption of 390 nW for a pixel-level ADC.

This study formulates and solves the wire planning problem with electro-migration and interference using an effective integer linear programming (ILP)-based approach. For circuits without obstacles, the proposed approach obtains a wire planning with the minimum wiring area. An effective approach for estimating the length of feasible routing wire is proposed to handle circuits with obstacles. In addition, the space reservation technique, which allocates the ring of the free silicon space around obstacles, is presented to improve interference among routing wires and on-obstacle wires. For circuits with obstacles, the proposed method minimizes total wiring area and reduces interference. Experimental results show that the integer linear-programming-based approach effectively and efficiently minimizes wiring area of routing wires.

We propose a data transmission method for resonant wireless power transmission systems. In order to transmit data, we use the coils originally designed for power transmission, no additional antennas are required. We focus on uplink data transmission and adopt the load modulation technique. This configuration yields mid-range data transmission without transmitting power. In addition, the proposal enables simultaneous power feeding and uplink data transmission. We make a prototype demonstrating resonant wireless power transmission and measure its S-parameter under some load conditions. The results confirm the potential of load modulation in supporting uplink data transmission. Additionally, the results are elucidated by analyzing an equivalent circuit. Measured S-parameter and equivalent circuit response are found to be similar.

A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.

An asynchronous sequential logic spiking neuron is an artificial neuron model that can exhibit various bifurcations and nonlinear responses to stimulation inputs. In this paper, a pulse-coupled system of the asynchronous sequential logic spiking neurons is presented. Numerical simulations show that the coupled system can exhibit various lockings and related nonlinear responses. Then, theoretical sufficient parameter conditions for existence of typical lockings are provided. Usefulness of the parameter conditions is validated by comparing with the numerical simulation results as well as field programmable gate array experiment results.

A fully differential high gain V-band three-stage transformer-coupled power amplifier (PA) is designed and implemented in 65 nm CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanism, single-ended to differential conversion, and input/inter-stage/output matching are used to facilitate a compact amplifier design. The design and optimization methodologies of active and passive devices are presented. With a cascode configuration, the amplifier achieves a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply, which compares favorably to recent published V-band PAs. The amplifier delivers 9 dBm and 13 dBm saturation output power (Psat) under 1 V and 1.5 V supplies, respectively, and occupies a core chip area of 0.05 mm2. The measurement results validate a high gain and area-efficient power amplifier design methodology in deep-scaled CMOS for applications in millimeter-wave communication.

Accurate device models are very important for the design of high-frequency circuits. One of the factors degrading the accuracy of device models appears during the de-embedding procedure. Generally, to obtain device characteristics without parasitic elements such as pads, a de-embedding procedure is essential. However, some errors are introduced during this procedure, which degrades the accuracy of device models. In this paper, we demonstrate that such errors due to de-embedding are cancelled in cascade circuit design, meaning that cascade circuits can be designed without knowing the actual characteristics of devices. Because it is difficult to know the actual characteristics of devices at a high frequency, the cancellation of the de-embedding error is expected to improve the accuracy of device models at high frequencies. After giving a theoretical treatment of de-embedding error cancellation, we report the results of simulations and measurements performed for verification.

This paper investigates characteristics of periodic structure of ferrite and dielectric slabs in cutoff waveguide which include left-handed operation. Transmission line model and finite element simulation are used to get dispersion characteristics and scattering parameters. Band pass response of left-handed ferrite mode at negative permeability region are discussed with backward wave phenomenon. Theoretical results show that by choosing appropriate ratio of (1) ferrite width and dielectric width, and (2) ferrite length and dielectric length, band pass response with steep edge characteristics can be obtained by the LH ferrite mode, which are confirmed with experiments using single crystal of yttrium iron garnet ferrite. Good band pass and phase shift responses are observed in S band.

This paper presents a 100–120-GHz pulse transmitter chip with a 5424 on-chip loop antenna array for the purpose of beam-formability in portable millimeter-wave (mm-wave) active imaging applications. We present a new idea for silicon-based mm-wave pulse beam-forming by using voltage-varied CMOS inverter chain. This 4-mm4-mm transmitter chip is designed and fabricated in a 2.5-V 0.25-µm 4-metal-layer Si-Ge Bi-CMOS process. The 30-µm30-µm loop antenna located on the top-metal layer operates as an coil in an integrated mm-wave pulse generator. Each of on-chip pulse generators employing under-damped/over-damped conditions to produce mm-wave pulses includes an R-L-C circuit, a bipolar junction transistor (BJT) operated as a switch and a CMOS inverter chain circuit for shaping the rising edge of the input clock. Simulation results by ADS 2009 and HSPICE show that loop antenna' inductance and resistance at 80–120-GHz are 51 pH and 3 Ω, respectively. A simulation performance of an integrated 136 loop antenna array illustrates the variation of maximum radiation angles depending on different phase values between array's elements. By using an mm-wave power meter, a 90–140-GHz standard horn antenna and a Schottky diode detector, several measured radiation patterns of this loop antenna array chip are achieved. From the measurement result, we demonstrate the possibility of an integrated mm-wave pulse generator for the purpose of beam-forming by changing power supplies of inverter chains.

This paper proposes a novel waveguide intersection separating two H-plane waveguide systems from each other. If a four-port network in a four-fold rotational symmetry is completely matched, it has necessarily intersection properties. The proposed waveguide intersection consists of a square H-plane waveguide planar circuit connected four input/output waveguide ports in a four-fold rotational symmetry, and several metallic posts inserted at the junction without destroying the symmetry to realize a perfect matching. By optimizing the circuit parameters, high isolation properties are obtained in a relatively wide frequency band of about 8.6% for return loss and isolation better than 20 and 30 dB, respectively, for a circuit designed at 10 GHz. The proposed waveguide intersection can be analyzed by H-plane planar circuit approach, and possess advantages of compactness, simplicity, and high-power handling capability. Furthermore, an SIW intersection is designed by applying H-plane planar circuit approach to a waveguide circuit filled with dielectric material, and high isolation properties similar to H-plane waveguide intersection can be realized. The validity of these design concepts is confirmed by em-simulations and experiments.

We present an 88 wavelength-routing switch (WRS) that monolithically integrates tunable wavelength converters (TWCs) and an 88 arrayed-waveguide grating. The TWC consists of a double-ring-resonator tunable laser (DRR TL) allowing rapid and stable switching and a semiconductor-optical-amplifier-based optical gate. Two different types of dry-etched mirrors form the laser cavity of the DRR TL, which enable integration of the optical components of the WRS on a single chip. The monolithic WRS performed 18 high-speed wavelength routing of a non-return-to-zero signal at 10 Gbit/s. The switching operation was demonstrated by simultaneously using two adjacent TWCs.

The paper is devoted to the experimental study of the arc plasma characteristics in SF6, N2 and CO2. To one flexible model of gas circuit breaker, short circuit experiments have been carried out considering the influence of contact gap (4–12 mm), gas pressure (1–5 atm), short circuit current (1–5 kA effective value) as well as gas species particularly. During the experiments, the arc image, arc current and arc voltage are recorded by the high speed camera, shunt and voltage transducer, respectively. It demonstrates that to the above mentioned three kinds of gases, the arc radius and arc voltage increase with the short circuit current and gas pressure normally; however, under the same experimental conditions, N2 arc holds the minimum arc radius and the maximum arc voltage, and the arc voltage of SF6 arc is the lowest.

An arc model has been applied in this paper to study the fundamental interruption environment of a 550 kV SF6 single-break tank circuit breaker. The full differential model takes into account of all important physical mechanisms and is implemented into a commercial Computational Fluid Dynamics (CFD) package, PHOENICS. The model takes a magneto-hydro-dynamics (MHD) approach and the governing equations are solved using the Finite Volume Method (FVM). Through the simulation, the flow velocity vector and mach number for capacitive current switching and short-circuit current breaking are analyzed, and flow dynamic characteristics are obtained. The simulation can provide helpful reference for the design of 550 kV SF6 single-break tank circuit breaker.

This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gate-bootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs based on slightly overlapped switching clocks. The interpolation, open-loop offset sampling, and two-step reference selection schemes for a back-end 6-bit flash ADC reduce both power consumption and chip area drastically compared to the conventional 6-bit flash ADCs. The prototype ADC in a 0.13 µm CMOS process demonstrates measured differential and integral non-linearities within 0.44LSB and 1.54LSB, respectively. The ADC shows a maximum SNDR and SFDR of 60.5 dB and 71.2 dB at 100 MS/s, respectively. The ADC with an active die area of 0.92 mm2 consumes 19 mW at 100 MS/s from a 1.0 V supply. The measured FOM is 0.22 pJ/conversion-step.

This paper studies a switched dynamical system based on the boost converter with a solar cell input. The solar cell is modeled by a piecewise linear current-controlled voltage source. A variant of peak-current-controlled switching is used in the boost converter. Applying the mapping procedure, the system dynamics can be analyzed precisely. As a main result, we have found an important example of trade-off between the maximum power point and stability: as a parameter (relates to the clock period) varies, the average power of a periodic orbit can have a peak near a period-doubling bifurcation set and an unstable periodic orbit can have the maximum power point.

This paper presents a novel charge transfer CMOS readout circuit for an X-ray time delay and integration (TDI) array with a depth of 64. In this study, a charge transfer readout scheme based on CMOS technology is proposed to sum 64 stages of the TDI signal. In addition, a dead pixel elimination circuit is integrated within a chip, thus resolving the weakness of TDI arrays related to defective pixels. The proposed method is a novel CMOS solution for large depth TDI arrays. Thus, a high signal-to-noise ratio (SNR) can be acquired due to the increased TDI depth. The readout chip was fabricated with a 0.6 µm standard CMOS process for a 15064 CdTe X-ray detector array. The readout circuit was found to effectively increase the charge storage capacity up to 1.6108 electrons, providing an improved SNR by a factor of approximately 8. The measured equivalent noise charge resulting from the readout circuit was 1.68104 electrons, a negligible value compared to the shot noise from the detector.

This paper presents an accurate and systematic method to simulate the interference imposed on the input/output (I/O) ports of electronic equipment under the electrical fast transients/burst (EFT/B) test. The equivalent circuit of the EFT/B generator and the coupling clamp are modeled respectively. Firstly, a transfer function (TF) of the EFT pulse-forming network is constructed with the latent parameters based on circuit theory. In the TF, two negative real parameters characterize the non-oscillation process of the network while one complex conjugate pair characterizes the damping-oscillation process. The TF of the pulse-forming network is therefore synthesized in the equivalent circuit of the EFT/B generator. Secondly, the standard coupling clamp is modeled based on the scatter (S) parameter obtained by using a vector network analyzer. By applying the vector fitting method during the rational function approximation, a macromodel of the coupling clamp can be obtained and converted to a Spice compatible equivalent circuit. Based on the aforementioned procedures, the interference imposed on the I/O ports can be simulated. The modeling methods are validated experimentally, where the interference in differential mode and common mode is evaluated respectively.

This paper develops planar circuit filters consisting of arbitrarily-shaped conductor patches and slots on a conductor-backed dielectric substrate, which are designed by an optimization technique based on the genetic algorithm. The developed filter has multiple resonators and their mutual couplings in the limited space by using both sides of the substrate, so that its compactness is realized. We first demonstrate the effectiveness of the present filter structure from some design samples numerically and experimentally. Then as a practical application, we design compact UWB filters, and their filter characteristics are verified from the measurements.