A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

This paper proposes a new chaos generator circuit with a current sampling scheme. This circuit generates an arbitrary nonlinear function corresponding to the time-domain current waveform supplied from an external source by using a pulse phase modulation approach. The measurement results of a fabricated chip with TSMC 0.25 µm process technology demonstrate that the proposed circuit can generate chaos signals even if D/A conversion is used for nonlinear waveform generation, because a current integral by sampling with a short pulse smooths the quantized nonlinear function.

Quantum circuits for elementary arithmetic operations are important not only for implementing Shor's factoring algorithm on a quantum computer but also for understanding the computational power of small quantum circuits, such as linear-size or logarithmic-depth quantum circuits. This paper surveys some recent approaches to constructing efficient quantum circuits for elementary arithmetic operations and their applications to Shor's factoring algorithm. It covers addition, comparison, and the quantum Fourier transform used for addition.

We fabricated a high-speed wavelength tunable arrayed-waveguide grating (AWG) and an AWG integrated with optical switches using (Pb,La)(Zr,Ti)O3-(PLZT). PLZT has a high electro-optic (EO) coefficient, which means these devices have considerable potential for use in reconfigurable optical add drop multiplexers (ROADMs). The PLZT waveguides in this work have a rib waveguide structure with an effective relative index difference (Δ) of 0.65%. Both AWGs have 8 channels with a frequency spacing of 500 GHz. The fabricated wavelength tunable AWGs allows us to freely shift the output at a particular wavelength to an arbitrary port by applying voltages to 3 mm long electrodes formed on each of the waveguides. We confirmed that the maximum tuning range with driving voltage of 22 V was approximately 32 nm at 1.55 µm. With the integrated 8-ch PLZT waveguide switch array, we could also select the output port by setting the drive voltage applied to the switch array. 2 2 directional coupler switches were used for the switch array. The two devices exhibited insertion losses of 17 dB and 19 dB, adjacent crosstalk of -18.5 dB and -19.7 dB, and a maximum extinction ratio of 19.6 dB and 12.6 dB, respectively. The tuning speed of both devices was 15 ns and their physical sizes were 9.0 23.0 mm and 8.0 29.5 mm, respectively.

In this paper, a novel 800 mV beta-multiplier reference current source circuit is presented. In order to cope with the narrow input common-mode range of the Opamp in the reference circuit, the resistive voltage divider was employed. High gain Opamp was designed to compensate for the intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18 µm CMOS process with nominal Vth of 420 mV and -450 mV for n-MOS and p-MOS transistor, respectively. The total power consumption including Opamp is less than 50 µW.

Quantum computations have so far proved to be more powerful than classical computations, but quantum computers still have not been put into practical use due to several technical issues. One of the most serious problems for realizing quantum computers is decoherence that occurs inevitably since our apparatus are surrounded with environment and open systems. In this paper, we give some surveys on a variety of effects of decoherence in quantum algorithms such as Grover's database search and quantum walks, and we show how quantum algorithms work under decoherence, how sensitive they are against decoherence, and how to implement a robust quantum circuit.

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65 nm and 130 nm CMOS technologies, respectively.

We analyze the carrier dynamics in MOSFETs under low-voltage operation. For this purpose the displacement (charging/discharging) current, induced during switching operations is studied experimentally and theoretically for a 90 nm CMOS technology. It is found that the experimental transient characteristics can only be well reproduced in the circuit simulation of low voltage applications by considering the carrier-transit delay in the compact MOSFET model. Long carrier transit delay under the low voltage switching-on operation results in long duration of the displacement current flow. On the other hand, the switching-off characteristics are independent of the bias condition.

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 µm BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.

Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are conducted with proposed model and Monte Carlo SPICE simulations. We successfully derived simple analytical formula on performance mismatch for analog CMOS circuits, which is verified to be accurate in using actual analog circuit design, within an average error of less than 10%.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

In advance of network communication society by the internet, the way how to send data fast with a little loss becomes an important transportation problem. A generalized maximum flow algorithm gives the best solution for the transportation problem that which route is appropriated to exchange data. Therefore, the importance of the maximum flow algorithm is growing more and more. In this paper, we propose a Maximum-Flow Neural Network (MF-NN) in which branch nonlinearity has a saturation characteristic and by which the maximum flow problem can be solved with analog high-speed parallel processing. That is, the proposed neural network for the maximum flow problem can be realized by a nonlinear resistive circuit where each connection weight between nodal neurons has a sigmodal or piece-wise linear function. The parallel hardware of the MF-NN will be easily implemented.

A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.

This paper proposes a scan design for delay fault testability of dual circuits. In normal operation mode, each proposed scan flip flop operates as a master-slave flip flop. In test mode, the proposed scan design performs scan operation using two scan paths, namely master scan path and slave scan path. The master scan path consists of master latches and the slave scan path consists of slave latches. In the proposed scan design, arbitrary two-patterns can be set to flip flops of dual circuits. Therefore, it achieves complete fault coverage for robust and non-robust testable delay fault testing. It requires no extra latch unlike enhanced scan design. Thus the area overhead is low. The evaluation shows the test application time of the proposed scan design is 58.0% of that of the enhanced scan design, and the area overhead of the proposed scan design is 13.0% lower than that of the enhanced scan design. In addition, in testing of single circuits, it achieves complete fault coverage of robust and non-robust testable delay fault testing. It requires smaller test data volume than the enhanced scan design in testing of single circuits.

This paper presents a hierarchical NoC architecture to support GT (Guaranteed Throughput) signals to process multimedia data in embedded systems. The architecture provides a communication environment that meets the diverse conditions of communication constraints among IPs in power and area. With a system based on packet switching, which requires storage/control circuits to support GT signals, it is hard to satisfy design constraints in area, scalability and power consumption. This paper proposes a hierarchical 444 mesh-type NoC architecture based on circuit switching, which is capable of processing GT signals requiring high throughput. The proposed NoC architecture shows reduction in area by 50.2% and in power consumption by 57.4% compared with the conventional NoC architecture based on circuit switching. These figures amount to by 72.4% and by 86.1%, when compared with an NoC architecture based on packet switching. The proposed NoC architecture operates in the maximum throughput of 19.2 Gb/s.

A new acceleration scheme that decreases the number of required iterations in relaxation methodology is proposed. The proposed scheme uses dynamic error prediction of an improved approximation to the solution during an iterative computation. The proposed scheme's application to circuit simulations required an average of 67.3% fewer iterations compared to un-accelerated relaxation methods.

This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

This paper reviews our recent progress on arrayed waveguide gratings (AWGs) using super-high-Δ silica-based planar lightwave circuit (PLC) technology and their application to integrated optical devices. Factors affecting the chip size of AWGs and the impact of increasing relative index difference Δ on the chip size are investigated, and the fabrication result of a compact athermal AWG using 2.5%-Δ silica-based waveguides is presented. As an application of super-high-Δ AWGs to integrated devices, a flat-passband multi/demultiplexer consisting of an AWG and cascaded MZIs is presented.

In this paper, a criterion for nonlinear stability analysis of microwave oscillator has been devised. The circuit envelope method has been used for analyzing the perturbed circuit. The proposed approach is evaluated by analyzing the nonlinear stability of a practical FET oscillator.