This paper describes the application techniques of the latency insertion method (LIM) to CMOS circuit simulations. Though the existing LIM algorithm to CMOS circuit performs fast transient analysis, CMOS circuits are not modeled accurately. As a result, they do not provide accurate simulations. We propose a more accurate LIM scheme for the CMOS inverter circuit by adopting a more accurate model of the CMOS inverter characteristics. Moreover, we present the way to expand the LIM algorithm to general CMOS circuit simulations. In order to apply LIM to the general CMOS circuits which consist of CMOS NAND and NOR, we derive the updating formulas of the explicit form of the LIM algorithm. By using the explicit form of the LIM scheme, it becomes easy to take in the characteristics of CMOS NAND and NOR into the LIM simulations. As a result, it is confirmed that our techniques are useful and efficient for the simulations of CMOS circuits.

The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.

In order to incorporate the reader/writers (RWs) into mobile electronic devices, miniaturization and flexibility are required. To meet these requirements, we fabricate an ultra-small RW with multiple contactless interfaces by mounting main unit circuits inside the antenna coil and using flexible multi-layer circuit board.

Though millimeter wave applications have attracted much attention in recent years, they have not yet been put to practical use. The major reason for the failure may be a large transmission loss peculiar to the short wavelength. In order to overcome the inconvenience, it may be promising to introduce the technology of millimeter-wave NRD-guide circuits. In this technology, not only NRD-guide but also Gunn diodes and Schottky diodes play the important role in high bit-rate millimeter-wave applications. A variety of practical millimeter wave wireless systems have been proposed and fabricated. Performances and applications of them are discussed in detail as well.

We propose a novel 50 Mb/s optical transmitter fabricated in a 0.6 µm BiCMOS technology for automotive applications. The proposed VCSEL driver chip was designed to operate with a single supply voltage ranging from 3.0 V to 5.25 V. A fully integrated feedforward current control circuit is presented to stabilize the optical output power without any external components. The experimental results show that the optical output power can be stable within a 1.1 dB range and the extinction ratio greater than 14 dB over the automotive environmental temperature range of -40 to 105.

This paper describes the characteristic of negative group delay (NGD) circuits for various configurations including first-order, distributed, and second-order RC circuit configurations. This study includes locus, magnitude, and phase characteristics of the NGD circuits. The simplest NGD circuit is available using first-order RC or RL configuration. As an example of distributed circuit configuration, it is verified that losses in a distributed line causes NGD characteristic at higher cut-off band of a coupled four-line bandpass filter. Also, novel wideband NGD circuits using second-order RC configuration, instead of conventional RLC configuration, are proposed. Adding a parallel resistor to a parallel-T filter enables NGD characteristic to it. Also, a Wien-Robinson bridge is modified to have NGD characteristic by controlling the voltage division ratio. They are fabricated on MMIC substrate, and their NGD characteristics are verified with measured results. They have larger insertion loss than multi-stage RLC NGD circuits, however they can realize second-order NGD characteristic without practical implementation of inductors.

Using the transient current switch circuit in parallel with the energizing switching contacts for timely control of breaking operation, the increase of contact voltage is suppressed at the last stage of the breaking of electric contacts. Breaking contact voltage Vc and current Ic of electromagnetic relays with Ag contacting electrodes were measured with 12.5-50 V and 0.1-20 A for two hinge springs (Spring constants; 2 N/mm and 0.2 N/mm). The current-decreasing process was clearly measured at the melting voltage Um. After Vc=Um, the breaking time of contact current did not depend on mechanical motion controlled by the two hinge springs and energizing power-supply voltage, but depended on the contact current. The residue of melt electrode was observed optically as a white fusion spot, with radius depending on the energizing current.

In this paper, a novel eight-way Ka-band spatial power combining structure based on SIW/HMSIW is presented and studied. The power-combining structure is realized by transitions between HMSIW and parallel multiport planar microstrip lines. The power combiner is designed and fabricated in 33.5-35 GHz. The measured results show a good agreement with simulation and a combining efficiency of 72% is achieved at 34.3 GHz.

A 0.18 µm 1.5 V/50 mA stability-enhanced low dropout regulator (LDO) is presented. A multi-path error amplifier and a split pass device structure are utilized for pole-zero pair compensation. The proposed LDO can be stable without a load capacitor and also stable with different combinations of load capacitors and equivalent series resistance.

Using the transient current switch circuit in parallel with the energizing contacts, the slow decay of the contact current due to thermal fusion of metal was observed just after the contact voltage exceeded the melting contact voltage Um. At that time, the contact voltage was higher than the boiling contact voltage Ub. These results contradict Holm's θ theory. A new melting model of breaking mechanical contact is proposed. The area surrounding a cluster of contacting a-spots melts, the melt metal diffuses, and the contact spot thermally shrinks. Including the metal phase transition from solid to liquid, the increase of contact resistance is introduced to the electric circuit analysis. The numerical analysis agrees qualitatively with measured V-I characteristics.

This paper proposes the design of a driver to deal with a thin-disc central supporting structure ultrasonic actuator based on the vibration modes and the equivalent circuit. In order to gain the electromechanical match at resonant frequency, a spectrum analyzer should measure admittance for driving piezoelectric ceramics. The virtual analyzer also investigated the characteristics of a MODEL-E equivalent circuit based upon the admittance-frequency response. The inherent capacitance from an ultrasonic actuator became the partial component in the design of a resonant circuit. IsSpice software is introduced to simulate as well as the experimental results has demonstrated a high agreement related to the conceptual design and practical implementation for the driving circuit.

This paper presents an accurate and systematic method to model the equivalent circuit of pulse generator in the electrical fast transients/burst test (EFT/B). Firstly, a new analytical expression is presented to express the generator's charging and discharging process under open-condition (1000-Ω), which all its coefficients are determined according to the output waveform specified by the manufacturer. And then, with adoption of the step source, the transfer function of the pulse forming network in Laplace domain is deduced, which is ready for the network synthesis. Based on above discussion, the parameterized method and the technique of constant-resistance are adopted for the network synthesis. Finally, the equivalent circuit is renormalized and improved to meet the specification under matching-condition (50-Ω). In this way, the equivalent circuit of EFT/B generator is obtained and can be adjusted conveniently to satisfy the different manufacturers. The PSPICE simulation with a certain load is validated by measurement.

This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5 V 0.7 µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

Printed circuit boards (PCBs) driven by a connected feed cable are considered to be one of the main sources of the electromagnetic interference (EMI) from electronic devices. In this paper, a method for predicting the electromagnetic (EM) radiation from a PCB driven by a connected feed cable at up to gigahertz frequencies is proposed and demonstrated. The predictive model is based on the transmission line theory and current- and voltage-driven CM generation mechanisms with consideration of antenna impedance. Frequency responses of differential-mode (DM) and common-mode (CM) currents and far-electric field were investigated experimentally and with finite-difference time-domain (FDTD) modeling. First, the dominant component in total EM radiation from the PCB was identified by using the Source-Path-Antenna model. Although CM can dominate the total radiation at lower frequencies, DM is the dominant component above 3 GHz. Second, the method for predicting CM component at lower frequencies is proposed. And its validity was discussed by comparing FDTD calculated and measured results. Specifically, the relationship between the CM current and the terminating resistor was focused as important consequence for the prediction. Good agreement between the measured and predicted results shows the validity of the predicted results. The proposed model can predict CM current with sufficient accuracy, and also identify the primary coupling-mechanism of CM generation. Then far-electric field was predicted by using the proposed method, and it was demonstrated that outline of the frequency response of the undesired EM radiation from the PCB driven by the connected feed cable can be predicted with engineering accuracy (within 6 dB) up to 18 GHz. Finally, as example of application of equivalent circuit model to EMC design, effect of the width of the ground plane was predicted and discussed. The equivalent circuit model provides enough flexibility for different geometrical parameters and increases our ability to provide insights and design guidelines.

Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.

An analytical method for estimating coupling between microstrip lines in arbitrary directions on adjacent layers in multi-layer printed circuit boards is studied: one line is embedded and the other is on the surface layer. Coupling or crosstalk has been estimated by development of a circuit-concept approach based on modified telegrapher's equations of the Agrawal approach instead of the Taylor approach for some computational advantages. Electromagnetic fields from the embedded microstrip line and the microstrip line on the surface can be obtained by using the electric image method for dielectric substrates. To verify the proposed approach, we conducted some experiments and compared the results of our approach with those of measurement and a commercial electromagnetic solver.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

A guard trace placed near a signal line reduces common-mode radiation from a printed circuit board. The reduction effect is evaluated by the imbalance difference model, which was proposed by the authors, when the guard trace has exactly the same potential as the return plane. However, depending on interval of ground connection of the guard trace, the radiation can increase when the guard trace resonates. In this paper, the authors show that the increase of radiation is caused by the common mode, and extend the imbalance difference model to explain a mechanism of increase of common-mode radiation. Additionally, the effective via location of the guard trace is proposed to reduce the number of vias. The guard trace voltage due to the resonance excites the common mode at the interface where the cross-sectional structure of the transmission line changes since the common-mode excitation is expressed by the product of the voltage and the difference of current division factors. To suppress the common-mode excitation, the guard trace should be grounded at the point where the cross-sectional structure changes. As a result, the common-mode radiation decreases even when the guard trace resonates.