This paper develops planar circuit filters consisting of arbitrarily-shaped conductor patches and slots on a conductor-backed dielectric substrate, which are designed by an optimization technique based on the genetic algorithm. The developed filter has multiple resonators and their mutual couplings in the limited space by using both sides of the substrate, so that its compactness is realized. We first demonstrate the effectiveness of the present filter structure from some design samples numerically and experimentally. Then as a practical application, we design compact UWB filters, and their filter characteristics are verified from the measurements.

This paper presents an accurate and systematic method to simulate the interference imposed on the input/output (I/O) ports of electronic equipment under the electrical fast transients/burst (EFT/B) test. The equivalent circuit of the EFT/B generator and the coupling clamp are modeled respectively. Firstly, a transfer function (TF) of the EFT pulse-forming network is constructed with the latent parameters based on circuit theory. In the TF, two negative real parameters characterize the non-oscillation process of the network while one complex conjugate pair characterizes the damping-oscillation process. The TF of the pulse-forming network is therefore synthesized in the equivalent circuit of the EFT/B generator. Secondly, the standard coupling clamp is modeled based on the scatter (S) parameter obtained by using a vector network analyzer. By applying the vector fitting method during the rational function approximation, a macromodel of the coupling clamp can be obtained and converted to a Spice compatible equivalent circuit. Based on the aforementioned procedures, the interference imposed on the I/O ports can be simulated. The modeling methods are validated experimentally, where the interference in differential mode and common mode is evaluated respectively.

Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100 Msps and 12 bit has been achieved with 10 mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38 mW at 300 MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

In this paper, a differential input/output linear MOS transconductor using an adaptively biasing technique is proposed. The proposed transconductor based on a differential pair is linearized by employing an adaptively biasing circuit. The linear characteristic of the individual differential output currents are obtained by introducing the adaptively biased currents to terminate the differential output terminals. Using the proposed technique, the common-mode rejection ration (CMRR) becomes high. Simulation results show that the proposed technique is effective for improvement of the linearity and other performances.

Many kinds of microstrip array antennas have been developed in the millimeter-wave band. In order to avoid feeding loss and the decrease of antenna gain by beam shift due to frequency changes, center-fed array antennas are advantageous. In this case, the element spacing around the feeding circuit of the transition from the waveguide to two microstrip lines is larger than one wavelength. Therefore, the sidelobe level grows significantly. In order to suppress the sidelobe level, we propose transitions with slot radiators. Moreover, any polarization angles can be achieved by changing the slot angle. A wide variety from 1.5% to 70% of slot radiator coupling powers can be achieved. To investigate the performance of the proposed transition, 10, 22 and 30-element center-fed microstrip comb-line antennas with the proposed transition were developed at 76.5 GHz, and measured performance was evaluated in the millimeter-wave band.

Different from distributed baluns, active baluns have group delay variations in the lower bands related to inherent internal capacitances and resistance in transistors. A negative group delay (NGD) circuit is employed as a compensator of group delay variation for an ultra-wideband (UWB) active balun. First, three-cell NGD circuit is inserted into a simple active balun circuit for realizing both group delay compensation and return loss improvement. The simulated results show a group delay variation of 4.8 ps and an input return loss of above 11.5 dB in the UWB band (3.1-10.6 GHz). Then, a pair of one-cell NGD circuits is added to reduce the remaining group delay variation (3.4 ps in simulation). The circuit with the NGD circuits was fabricated on an InGaP/GaAs HBT MMIC substrate. The measured results achieved a group delay variation of 7.7 ps, a gain variation of 0.5 dB, an input return loss of greater than 10 dB, and an output return loss of larger than 8.1 dB in the UWB band.

A fifth-order switched-capacitor (SC) complex filter was implemented in 0.2-µm CMOS technology. A novel SC integrator was developed to reduce the die size and current consumption of the filter. The filter is centered at 24.730.15 kHz (3δ) and has a bandwidth of 20.260.3 kHz (3δ). The image channel is attenuated by more than 42.6 dB. The in-band third-order harmonic input intercept point (IIP3) is 17.3 dBm, and the input referred RMS noise is 34.3 µVrms. The complex filter consumes 350 µA with a 2.0-V power supply. The die size is 0.578 mm2. Owing to the new SC integrator, the filter achieves a 27% reduction in die size without any degradation in its characteristics, including its noise performance, compared with the conventional equivalent.

In this paper, we propose a robust state estimation method using a particle filter (PF) for a class of nonlinear systems which have stochastic parameter uncertainties. A robust PF was designed using prediction and correction structure. The proposed PF draws particles from a simple proposal density function and corrects the particles with particle-wise correction gains. We present a method to obtain an error variance of each particle and its upper bound, which is minimized to determine the correction gain. The proposed method is less restrictive on system nonlinearities and noise statistics; moreover, it can be applied regardless of system stability. The effectiveness of the proposed robust PF is illustrated via an example based on Chua's circuit.

High-power protection switch utilizing a new stub/line selectable configuration is presented. By employing the proposed circuit topology, the insertion loss at receiving mode and the power handling capability at transmitting mode can be independently designed. Therefore, the proposed circuit is able to achieve low insertion loss at receiving mode while keeping high-power performance at transmitting mode. To verify this methodology, MMIC switch has been fabricated in Ka-band. The circuit has achieved the insertion loss of 2 dB, the isolation of 25 dB, and the power handling capability of 40 dBm at 5% bandwidth.

This paper presents a resistor-compensation technique for a CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in the 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. The measurements verify a current reference of 735.6 nA, the voltage reference of 888.1 mV, and the power consumption of 91.28 µW at a supply voltage of 3.3 V. The voltage TC is 49 ppm/ in the temperature range from 0 to 100 and 12.8 ppm/ from 30 to 100. The current TC is 119.2 ppm/ at temperatures of 0 to 100. Measurement results also demonstrate a stable voltage reference at high temperature (> 30), and a constant current reference at low temperature (< 70).

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

In this paper, we present a 0.18-µm CMOS fully integrated X-band shock wave generator (SWG) with an on-chip dipole antenna and a digitally programmable delay circuit (DPDC) for pulse beam-formability in short-range and hand-held microwave active imaging applications. This chip includes a SWG, a 5-bit DPDC and an on-chip wide-band meandering dipole antenna. By using an integrated transformer, output pulse of the SWG is sent to the on-chip meandering dipole antenna. The SWG operates based on damping conditions to produce a 0.4-V peak-to-peak (p-p) pulse amplitude at the antenna input terminals in HSPICE simulation. The DPDC is designed to adjust delays of shock-wave outputs for the purpose of steering beams in antenna array systems. The wide-band dipole antenna element designed in the meandering shape is located in the top metal of a 5-metal-layer 0.18-µm CMOS chip. By simulating in Momentum of ADS 2009, the minimum value of antenna's return loss, S 11, and antenna's bandwidth (BW) are -19.37 dB and 25.3 GHz, respectively. The measured return loss of a stand-alone integrated meandering dipole is from -26 dB to -10 dB with frequency range of 7.5-12 GHz. In measurements of the SWG with the integrated antenna, by using a 20-dB standard gain horn antenna placed at a 38-mm distance from the chip's surface, a 1.1-mVp-p shock wave with a 9-11-GHz frequency response is received. A measured 3-ps pulse delay resolution is also obtained. These results prove that our proposed circuit is suitable for the purpose of fully integrated pulse beam-forming system.

With the process technological progress in recent years, low voltage power supplies have become quite predominant. With this, the voltage margin has decreased and therefore the power/ground design that satisfies the voltage drop constraint becomes more important. In addition, the reduction of the power/ground total wiring area and the number of layers will reduce manufacturing and designing costs. So, we propose an algorithm that satisfies the voltage drop constraint and at the same time, minimizes the power/ground total wiring area. The proposed algorithm uses the idea of a network algorithm [1] where the edge which has the most influence on voltage drop is found. Voltage drop is improved by changing the resistance of the edge. The proposed algorithm is efficient and effectively updates the edge with the greatest influence on the voltage drop. From experimental results, compared with the conventional algorithm, we confirmed that the total wiring area of the power/ground was reducible by about 1/3. Also, the experimental data shows that the proposed algorithm satisfies the voltage drop constraint in the data whereas the conventional algorithm cannot.

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

A novel design technique for two-dimensional (2-D) waveguide slot arrays is proposed in this paper that combines a full-wave method of moments (MoM) analysis and an equivalent circuit with the explicit restraint of input matching. The admittance and slot spacing are determined first in an equivalent circuit to realize the desired distribution of power dissipation and phase, with the explicit restraint of input matching. Secondly by applying a full-wave MoM analysis to the finite 2-D array, slot parameters are iteratively determined to realize the active admittance designed above where slot mutual coupling and wall thickness are fully taken into account. The admittance, treated as the key parameter in the equivalent circuit corresponds to the power dissipation of the slots but not to the slot voltage, which is directly synthesized from the radiation pattern. The initial value of the power dissipation is assumed to be proportional to the square of the amplitude of the desired slot voltage. This assumption leads to a feedback procedure, because the resultant slot voltage distribution generally differs from the desired ones due to the effect of non-uniformity in the characteristic impedance on slot apertures. This slot voltage error is used to renew the initial distribution of power dissipation in the equivalent circuit. Generally, only one feedback cycle is needed. Two 2427-element arrays with uniform and Taylor distributions were designed and fabricated at 25.3 GHz. The measured overall reflections for both antennas were suppressed below -18 dB over the 24.3-26.3 GHz frequency range. High aperture efficiencies of 86.8% and 55.1% were realized for the antennas with uniform and Taylor distributions, the latter of which has very low sidelobes below -33 dB in both the E- and H-planes.

The long-standing problem of predicting circuit performance variations without a huge number of statistical investigations is demonstrated to be solvable by a surface-potential-based MOSFET model. Direct connection of model parameters to physical device parameters reflecting process variations and the reduced number of model parameters are the enabling key model properties. It has been proven that the surface-potential-based model HiSIM2 is capable of reproducing measured I-V and its derivatives' variations with those of device/process related model parameters. When used to predict 51-stage ring oscillator frequency variation including both inter- and intra-chip variation, it reproduces measurements with shortened simulation time.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.