In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

A 32bit CPU, which can operate more than 15 years with 220mAH Li battery, or eternally operate with an energy harvester of in-door light is presented. The CPU was fabricated by using 65nm SOTB CMOS technology (Silicon on Thin Buried oxide) where gate length is 60nm and BOX layer thickness is 10nm. The threshold voltage was designed to be as low as 0.19V so that the CPU operates at over threshold region, even at lower supply voltages down to 0.22V. Large reverse body bias up to -2.5V can be applied to bodies of SOTB devices without increasing gate induced drain leak current to reduce the sleep current of the CPU. It operated at 14MHz and 0.35V with the lowest energy of 13.4 pJ/cycle. The sleep current of 0.14µA at 0.35V with the body bias voltage of -2.5V was obtained. These characteristics are suitable for such new applications as energy harvesting sensor network systems, and long lasting wearable computers.