FM converted CATV and super high frequency satellite TV signal transmission using lithium niobate Mach-Zehnder optical SSB modulator is proposed and demonstrated. Simultaneous FM-converted 40 CATV signal carriers (from 93 to 375 MHz) and 104 super high frequency satellite TV signal carriers (from 11.7 to 20.2 GHz) could be transmitted with good noise properties and distortion quality over 40 km of dispersive SMF with chromatic dispersion of 680 ps/nm. We clarify the required phase and power values by experiments on the relationship between sideband suppression ratio (SSR) and the phase/power to LN MZ optical SSB modulator. For instance, the absolute value of phase and power should be less than 5 degrees and 0.4 dB, respectively, to obtain SSR values above 35 dB.

A fully integrated 5.8 GHz ETC transceiver LSI has been developed. The transceiver consists of LNA, down-conversion MIX, ASK detector, ASK modulator, DA VCO, and ΔΣ-fractional-N PLL. The features of the transceiver are integrated matching circuitry for LNA input and for DA output, ASK modulator with VGA for local signal control to avoid local leakage and to keep suitable modulation index, and LO circuitry consisting of ΔΣ-fractional-N PLL and interference-robust ∞-shape inductor VCO to diminish magnetic coupling from any other circuitry. Use of these techniques enabled realization of the input and output VSWR of less than 1.25, modulation index of over 95%, and enough qualified TX signals. This transceiver was manufactured by 1P3M SiGe-BiCMOS process with 47 GHz cut-off frequency.

One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage Vdd, stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-µm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V Vdd.

The trend of microwave circuits has been toward highly integrated systems. Most design tools for designing microwave circuits mounted the linear or the nonlinear devices adopt the fundamental circuit theory using the S matrix on the frequency domain. The harmonic balance method is also used to correspond to the nonlinear circuit. Therefore, the effect of the electromagnetic field, for example, a mutual coupling between sub-circuits through the space is almost disregarded. To calculate these circuits included its surrounding electromagnetic field, the finite difference time domain method combined with the equivalent circuit simulation had been presented as the lumped element FDTD (LE-FDTD) method. In general, even if an analytical target is a linear circuit, the FDTD method requires very long analytical time. In this paper, we propose an efficient LE-FDTD method to reduce the analytical time. We investigate its efficiency to compare with the conventional LE-FDTD method or measurements, consequently, it is confirmed that the proposal method requires only at analytical time of 1/10 compared with the conventional method. We also show that the proposal method is able to analyze characteristics of the active integrated antenna (AIA) which are practicably impossible to analyze by using the conventional method.

An integration of the access/backbone network is expected to become indispensable in the future. We analyze the current and future optical networks and we describe the promising technologies. GMPLS architecture in backbone networks and WDM PON architecture in access networks will play the most important roles. We overview recent studies on the access/backbone integrated network to achieve guaranteed QoS. We also describe the developed system architecture as a milestone toward the access/backbone integrated network.

As a powerful computational test for nonexistence of a DC solution of a nonlinear circuit, the LP test is well-known. This test is useful for finding all solutions of nonlinear circuits; it is also useful for verifying the nonexistence of a DC operating point in a given region where operating points should not exist. However, the LP test has not been widely used in practical circuit simulation because the programming is not easy for non-experts or beginners. In this paper, we propose a new LP test that can be easily implemented on SPICE without programming. The proposed test is useful because we can easily check the nonexistence of a solution using SPICE only.

For the optimization design of air circuit breaker (ACB), it is important and necessary to calculate the electro-dynamic repulsion force acting on the movable contact. A method based on 3-D FEM with the equations that describe the relationships among current, magnetic field and repulsion force, which takes the ferromagnet into account, is adopted to calculate the electro-dynamic repulsion force. The method enables one to analyze the factors that affect the electro-dynamic repulsion force, including the number of the movable conductor parallel branches as well as the location of the axis and the shape of the flexible connection. The discussion of the calculation results is also presented in this paper.

This paper describes two different types of GaAs-HBT compatible, base-collector diode 0/20-dB step attenuators--diode-linearizer type and harmonics-trap type--for 3.5-GHz-band wireless applications. The two attenuators use an AC-coupled, stacked type diode switch topology featuring high power handling capability with low bias current operation. Compared to a conventional diode switch topology, this topology can improve the capability of more than 6 dB with the same bias current. In addition, successful incorporation of a shunt diode linearizer and second- and third-harmonic traps into the attenuators gives the IM3 distortion improvement of more than 7 dB in the high power ranging from 16 dBm to 18 dBm even in the 20-dB attenuation mode when IM3 distortion levels are basically easy to degrade. Measurement results show that both the attenuators are capable of delivering power handling capability (P0.2 dB) of more than 18 dBm with IM3 levels of less than -35 dBc at an 18-dBm input power while drawing low bias currents of 3.8 mA and 6.8 mA in the thru and attenuation modes from 0/5-V complementary supplies. Measured insertion losses of the linearizer-type and harmonics-trap type attenuators in the thru mode are as low as 1.4 dB and 2.5 dB, respectively.

A two-dimensional compressible magnetohydrodynamic (MHD) computational model has been developed to study the effect of gassing material on air arc behavior in low voltage circuit breaker. The properties of arc plasma and the electric, magnetic and radiative phenomena have been taken into account in the model. Based on the model, steady state solutions have been performed to study the effect of gassing material on the arc radius and electric field in the arc column. Then, the effect of gassing material on the transient process of arc motion also has been simulated. In addition, using the two-dimensional optical fiber measurement system, experiments have been done to measure the average velocity of arc motion with one model chamber and to verify the simulation model and prediction results. It demonstrates that the action of gassing material may yield the stronger electric field, less arc radius and higher arc motion velocity.

Eddy-current type proximity sensor is a non-contact type sensing device to detect the approach of a conductor by increase of coil resistance due to eddy-current loss. This paper proposes to add the cap-shaped magnetic flux shield at the top of the ferrite core for the actual sensor. In conventional proximity sensors, main magnetic flux path passes through the air between the target conductor and ferrite core. Proposed sensor, in contrast, has closed magnetic circuit geometry. It means that main magnetic flux path is almost completed by the core and the shield. Therefore, it is predicted that flux does not reach the target conductor and it causes debasement of sensing property. However, it is shown that the calculated results by FEM and measured results of sensing property of the proposed sensor is enhanced compared with the actual sensor. This paper quantitatively accounts the electromagnetisms of the proposed sensor from sensing property, flux distributions and eddy-current loss in each part of the sensor body. Moreover, material characteristics for the proposed shield, such as relative permeability and conductivity, are found.

This paper presents a novel method to increase an impedance of a current source. The proposed circuit with a cascode and gain-boosting configuration is also presented. The operation has been confirmed by simulation using a 0.18 µm CMOS technology.

Power supply noise waveforms are acquired in a voltage domain by an on-chip monitor at resolutions of 0.3 ns/1.2 mV, in a digital test circuit consisting of 0.18-µm CMOS standard logic cells. Concurrently, magnetic field variation on a printed circuit board (PCB) due to power supply current of the test circuit is measured by an off-chip magnetic probing technique. An equivalent circuit model that unifies on- and off-chip impedance network of the entire test setup for EMI analysis is used for calculating the on-chip voltage-mode power supply noise from the off-chip magnetic field measurements. We have confirmed excellent consistency in frequency components of power supply noises up to 300 MHz among those derived by the on-chip direct sensing and the off-chip magnetic probing techniques. These results not only validate the state-of-the art EMI analysis methodology but also promise its connectivity with on-chip power supply integrity analysis at the integrated circuit level, for the first time in both technical fields.

This paper presents an automated design of linear and non-linear differential analog circuits accelerated by reuse of genetic operations. The system first synthesizes circuits using pairs of simplified MOSFET model. During the evolutionary process, genetic operations that improve circuit characteristics are stored in a database and reused to effectively obtain a better circuit. Simplified elements in a generated circuit are replaced by MOSFETs and optimization of the transistor size is performed using an optimizer available in market if necessary. The capability of this method is demonstrated through experiments of synthesis of a differential voltage amplifier, a circuit having cube-law characteristic in differential mode and square-law characteristic in common-mode, and a dB-linear VGA (Variable Gain Amplifier). The results show the reuse of genetic operations accelerates the synthesis and success rate becomes 100%.

A new method of cancellation of IM3 using current feedback has been proposed for a multi-stage RFIC amplifier. In order to cancel the IM3 present in an output signal of the amplifier, the IIP3 level and IM3 phase of the amplifier are adjusted by means of feedback circuit techniques, so that the target specification is satisfied. By estimating the IIP3 level and IM3 phase variations for two states in situations with and without feedback possessing linear factors, the parameters of a feedback circuit can be calculated. To confirm the validity of the method, we have investigated two approaches; one including an analytical approach to designing a two-stage feedback amplifier, achieving an IIP3 level improvement of 14.8 dB. The other method involves the fabrication of single-stage amplifiers with and without feedback, operating at 850 MHz, both of which were designed as an integrated circuit using a 0.18 µm SiGe BiCMOS process. The fabricated IC's were tested using a load-pull measurement system, and a good agreement between the estimated and measured IIP3 level and IM3 phase variations has been achieved. Further studies show that the error in these variations, as estimated by the method, has been found to be less than 1.5 dB and 15 degrees, respectively, when the load admittance at 1701 MHz was greater than 1/50 S.

A 5-GHz-band highly linear frequency tuning voltage-controlled oscillator (VCO) using 0.35 µm SiGe BiCMOS technology is presented. The highly linear VCO has a novel resonant circuit that includes two spiral inductors, p-n junction diode varactor units and a voltage-level- shift circuit. The fabricated VCO exhibits a VCO gain from 224 to 341 MHz/V, giving a Kvco ratio of 1.5, which is less than one-half of that of a conventional VCO. The measured phase noise is -116 dBc/Hz at 1 MHz offset at an oscillation frequency of 5.5 GHz. The tuning range is from 5.45 to 5.95 GHz. The dc current consumption is 3.4 mA at a supply voltage of 3.0 V.

A quadrature demodulator (QDEMOD) for WCDMA direct-conversion receiver using a common-base input stage is reported. A common-base input stage is robust to parasitic elements and is suitable for integrating on-chip matching circuits to realize small and low-cost RF front-end modules. However, a common-mode blocker signal, such as the transmitter (TX) leakage signal, degrades the noise performance due to DC current increase and intermodulation distortion of the TX leakage signal and noise. We propose a QDEMOD with a common-base input stage capable of suppressing the TX leakage signal using symmetrical inductors. The QDEMOD was fabricated using SiGe BiCMOS process with fT of 75 GHz. The measured results show that the NF degradation does not occur until the TX leakage signal input is larger than -10 dBm.

An 8ch, 400 GHz monolithically integrated WDM channel selector featuring an array of quantum well semiconductor optical amplifiers (SOA) and arrayed waveguidegrating demultiplexer is presented. Reduction of fabrication complexity was achieved by using a single step selective area MOVPE to realize the different bandgap profiles for the SOA array and passive region. The selective growth mask dimensions were optimized by simulation. Dry-etching with short bending radii of 200 µm resulted in compact device size of 7 mm2.5 mm. Static channel selection with high ON-OFF ratio of >40 dB was achieved.

Lately, time-multiplexed I/Os for multi-device implementations (e.g., multi-FPGA systems), have come into practical use. They realize multiple I/O signal transmissions between two devices in one system clock cycle using one I/O wire between the devices and multiple I/O clock cycles. Though they ease the limitation of the number of I/O-pins of each device, the system clock period becomes much longer approximately in proprotion to the maximum number of multiplexed I/Os on a signal path. There is no conventional partitioning algorithm considering the effect of time-multiplexed I/Os directly. We introduce a new cost function for evaluating the suitability of a bipartition for multi-device implementations with time-multiplexed I/Os. We propose a performance-driven bipartitioning method VIOP which minimizes the value of the cost function. Our method VIOP combines three algorithms, such that i) min-cut partitioning, ii) coarse performance-driven partitioning, iii) fine performance-driven partitioning. For min-cut partitioning and coarse performance-driven partitioning, we employ a well-known conventional bipartitioning algorithms CLIP-FM and DUBA, respectively. For fine performance-driven partitioning for the final improvement of a partition, we propose a partitioning algorithm CAVP. By our method VIOP, the average cost was improved by 10.4% compared with the well-known algorithms.

This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.