Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation
Summary :
One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage Vdd, stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-µm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V Vdd.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.9 pp.1702-1707
- Publication Date
- 2007/09/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.9.1702
- Type of Manuscript
- Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology)
- Category
- Active Devices/Circuits
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Noboru ISHIHARA, "Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 9, pp. 1702-1707, September 2007, doi: 10.1093/ietele/e90-c.9.1702.
Abstract: One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage Vdd, stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-µm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V Vdd.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.9.1702/_p
Copy
@ARTICLE{e90-c_9_1702,
author={Noboru ISHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation},
year={2007},
volume={E90-C},
number={9},
pages={1702-1707},
abstract={One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage Vdd, stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-µm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V Vdd.},
keywords={},
doi={10.1093/ietele/e90-c.9.1702},
ISSN={1745-1353},
month={September},}
Copy
TY - JOUR
TI - Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1702
EP - 1707
AU - Noboru ISHIHARA
PY - 2007
DO - 10.1093/ietele/e90-c.9.1702
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2007
AB - One of the interesting submicron MOS FET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF MOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage Vdd, stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5 GHz amplifier has been designed and fabricated by using 0.18-µm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB from 1.2 to 2.9 V Vdd.
ER -
English
