A delay-compensation circuit for low-power subthreshold digital circuits is proposed. Delay in digital circuits operating in the subthreshold region of MOSFETs changes exponentially with process and temperature variations. Threshold-voltage monitoring and supply-voltage scaling techniques are adopted to mitigate such variations. The variation in the delay can be significantly reduced by monitoring the threshold voltage of a MOSFET in each LSI chip and exploiting the voltage as the supply voltage for subthreshold digital circuits. The supply voltage generated by the threshold voltage monitoring circuit can be regarded as the minimum supply voltage to meet the delay constraint. Monte Carlo SPICE simulations demonstrated that a delay-time variation can be improved from having a log-normal to having a normal distribution. A prototype in a 0.35-µm standard CMOS process showed that the exponential delay variation with temperature of the ring-oscillator frequency in the range from 0.321 to 212 kHz can remain by using compensation in the range from 5.26 to 19.2 kHz.

High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

Due to the difficulty of test pattern generation for sequential circuits, several design-for-testability (DFT) approaches have been proposed. An improvement to these current approaches is needed to cater to the requirements of today's more complicated chips. This paper introduces a new DFT method applicable to high-level description of circuits, which optimally utilizes existing functional elements and paths for test. This technique, called F-scan, effectively reduces the hardware overhead due to test without compromising fault coverage. Test application time is also kept at the minimum. The comparison of F-scan with the performance of gate-level full scan design is shown through the experimental results.

A neuro fuzzy method to design analog circuits is explained, where the universe of discourse of the fuzzy system is adjusted by means of a self-organized artificial neural network. As an example of this approach, an op-amp is optimized in order to hold a predetermined aim; where the unity gain bandwidth is an objective of design, and the restrictions of open-loop gain and margin phase are treated as objectives too. Firstly, the experience of the behavior of the circuit is obtained, hence an inference system is constructed and a neural network is applied to achieve a faster convergence into a desired solution. This approach is characterized by having a simple implementation, a very natural understanding and a better performance than static methods of fuzzy optimization.

A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.

A design methodology of Random Switching Logic (RSL) using CMOS standard cell libraries is proposed to counter power analysis attacks against cryptographic hardware modules. The original RSL proposed in 2004 requires a unique RSL-gate for random data masking and glitch suppression to prevent secret information leakage through power traces. In contrast, our new methodology enables to use general logic gates supported by standard cell libraries. In order to evaluate its practical performance in hardware size and speed as well as resistance against power analysis attacks, an AES circuit with the RSL technique was implemented as a cryptographic LSI using 130-nm and 90-nm CMOS standard cell library. From the results of attack experiments that used a million traces, we confirmed that the RSL-AES circuit has very high DPA and CPA resistance thanks to the contributions of both the masking function and the glitch suppressing function.

We edit in this paper several archives on the research and development in the field of microwave circuit technology in Japan, that originated with the invention of Yagi-Uda antenna in 1925, together with generally unknown historical topics in the period from the 1920s up until the end of World War II. As the main subject, we investigate the origin and evolution of the Multiply Split-Anode Magnetron, and clarify that the basic magnetron technology had been established until 1939 under the direction of Yoji Ito in cooperation of expert engineers between the Naval Technical Institute (NTI) and the Nihon Musen Co., while the Cavity Magnetron was invented by Shigeru Nakajima of the Nihon Musen Co. in May 1939, and further that physical theory of the Multiply Split-Anode Cavity Magnetron Oscillation and the design theory of the Cavity Magnetron were established in collaboration between the world-known physicists and the expert engineers at the NTI Shimada Laboratory in the wartime. In addition, we clarify that Sin-itiro Tomonaga presented the Scattering Matrix representation of Microwave Circuits, and others. The development mentioned above was carried out, in strict secrecy, in an unusual wartime situation up until 1945.

This paper presents two circuits to measure pulse width distribution of single event transients (SETs). We first review requirements for SET measurement in accelerated neutron radiation test and point out problems of previous works, in terms of time resolution, time/area efficiency for obtaining large samples and certainty in absolute values of pulse width. We then devise two measurement circuits and a pulse generator circuit that satisfy all the requirements and attain sub-FO1-inverter-delay resolution, and propose a measurement procedure for assuring the absolute width values. Operation of one of the proposed circuits was confirmed by a radiation experiment of alpha particles with a fabricated test chip.

Ambient light sensors have been used to reduce power consumption of Active Matrix Liquid Crystal Displays (AMLCD) adjusting display brightness depending on ambient illumination. Discrete sensors have been commonly used for this purpose. They make module design complex. Therefore it has been required to integrate the sensors on the display panels for solving the issue. So far, many kinds of integrated sensors have been developed using Amorphous Silicon (a-Si) technology or Low Temperature Polycrystalline Silicon (LTPS) technology. These conventional integrated sensors have two problems. One is that LTPS sensors have less dynamic range due to the less photosensitivity of LTPS photodiodes. The other is that both the LTPS and a-Si sensors are susceptible to display driving noises. In this paper, we introduce a novel integrated sensor using both LTPS and a-Si technologies, which can solve these problems. It consists of vertical a-Si Schottky photodiodes and an LTPS differential converter circuit. The a-Si photodiodes have much higher photosensitivity than LTPS ones, and this contributes to wide dynamic range and high accuracy. The LTPS differential converter circuit converts photocurrent of the photodiodes to a robust digital signal. In addition it has a function of canceling the influences of the display driving noises. With the circuit, the sensor can stably and accurately work even under the noises. The performance of the sensor introduced in this paper was measured to verify the advantages of the novel design. The measurement result showed that it worked in a wide ambient illuminance range of 5-55,000 lux with small errors of below 5%. It was also verified that it stably and accurately worked even under the display driving noise. Thus the sensor introduced in this paper achieved the wide dynamic range and noise robustness.

We developed a slotted waveguide planer array antenna with partially parallel feeding in millimeter-wave band. Travelling-wave excitation is more effective for low loss feeding of array antennas than parallel feeding systems. However, array antenna with travelling-wave excitation essentially possesses a significant problem of long line effect which degrades gain due to beam shift by frequency change when the array antenna is fed from the edge of the radiating waveguide. We propose the way to reduce the gain degradation due to frequency change, thus, partially parallel feeding system is developed. Measured performance of the developed antenna is evaluated in this paper.

Narrow-wall-connected microstrip-to-waveguide transition using V-shaped patch element in millimeter-wave band is proposed. Since the microstrip line on the narrow-wall is perpendicular to the E-plane of the waveguide, waveguide field does not couple directly to the microstrip line. The current on the V-shaped patch element flows along inclined edges, then current on the V-shaped patch element couples to the microstrip line efficiently. Three types of transitions are investigated. A numerical investigation of these transitions show some relations between bandwidth and insertion loss. It is confirmed that the improved transition exhibits an insertion loss of 0.6 dB from 76 to 77 GHz, and a bandwidth of 4.1% (3.15 GHz) for the reflection coefficient below -15 dB.

In this letter a new active element the Current Follower Transconductance Amplifier (CFTA) for the realization of the current-mode analog blocks is presented. The element is a combination of the Current Follower (CF) and the Balanced Output Transconductance Amplifier (BOTA). Possible internal structure of the CFTA is presented. The usage of the new active element is shown on the design of the Kerwin-Huelsman-Newcomb (KHN) structure working in the current mode. The frequency filter using the CFTA elements has been designed using the signal-flow graphs. The circuit structure employs three CFTA elements and two grounded passive elements. The filter enables realizing not only the basic functions as the low- (LP), band- (BP) and high-pass (HP) but also the notch and all-pass (AP) filter. The advantage of the structure presented is that the outputs of the filter are at high impedance and hence it is not necessary to use other auxiliary active elements. The properties of the filter proposed were verified by sensitivity and AC analyses in the PSPICE program.

We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.

Adjustability is an important function of the magnetic release for modern molded case circuit breakers. Based on virtual prototype technology, an automatic prediction method is proposed to design reasonable reactive spring parameters for this kind of magnetic release. 3-D finite element method is adopted to calculate the static characteristics of the magnetic release. Then the dynamic characteristics of the magnetic release can be simulated taking into account the variation of the spring parameters with multi-dynamics method. The calculation results have been verified by the relevant experiments. It demonstrates that the proposed method is feasible to perform the design task.

Similarities and differences of the thermal analysis issues between the intelligent and general AC contactors are analyzed. Heat source model of the magnet system is established according to the unique control mode of the intelligent AC contactor. Linking with the features common of the two kinds of contactors, the extension of the thermal analysis method of the general AC contactor to the intelligent AC contactor is demonstrated. Consequently, a comprehensive thermal analysis model considering heat sources of both main circuit and magnet system is constructed for the intelligent AC contactor. With this model, the steady-state temperature rise of the intelligent AC contactor is calculated and compared with the measurements of an actual intelligent AC contactor.

This paper represents a low noise second harmonic oscillator using mutually synchronized Gunn diodes. A multi-layer MIC technology is adopted to reduce the circuit size of the oscillator. The oscillator consists of Gunn diodes, slot line resonators and strip lines. By embedding Gunn diodes in the slot line resonators, a harmonic RF signal can be generated very easily. The strip lines are used for the power combining output circuit. The shape of slot line resonator is square in order to achieve the low phase noise and the suppression of undesired harmonics. The second harmonic oscillator is designed and fabricated in K band. The output power is +8.89 dBm at the design frequency of 18.75 GHz (2f0) with the phase noise of -116.2 dBc/Hz at the offset frequency of 1 MHz. Excellent suppression of the undesired fundamental frequency signal (f0) of -33 dBc is achieved. Also, the circuit size is reduced by three-tenths relative to that of the previously proposed circuit.

A new pipeline controller based on the Early Acknowledgement (EA) protocol is proposed for bundled-data asynchronous circuits. The EA protocol indicates acknowledgement by the falling edge of the acknowledgement signal in contrast to the 4-phase protocol, which indicates it on the rising edge. Thus, it can hide the overhead caused by the resetting period of the handshake cycle. Since we have designed our controller assuming several timing constraints, we first analyze the timing constraints under which our controller correctly works and then discuss their appropriateness. The performance of the controller is compared both analytically and experimentally with those of two other pipeline controllers, namely, a very high-speed 2-phase controller and an ordinary 4-phase controller. Our controller performs better than a 4-phase controller when pipeline has processing elements. We have obtained interesting results in the case of a non-linear pipeline with a Conditional Branch (CB) operation. Our controller has slightly better performance even compared to 2-phase controller in the case of a pipeline with processing elements. Its superiority lies in the EA protocol, which employs return-to-zero control signals like the 4-phase protocol. Hence, our controller for CB operation is simple in construction just like the 4-phase controller. A 2-phase controller for the same operation needs to have a slightly complicated mechanism to handle the 2-phase operation because of the non-return-to-zero control signals, and this results in a performance overhead.

In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.