A ripple-free dual-rate control system is designed for a single-input single-output dual-rate system, in which the sampling interval of a plant output is longer than the holding interval of a control input. The dual-rate system is converged to a multi-input single-output single-rate system using the lifting technique, and a control system is designed based on an error system using the steady-state variable. Because the proposed control law is designed so that the control input is constant in the steady state, the intersample output as well as the sampled output converges to the set-point without both steady-state error and intersample ripples when there is neither modeling nor disturbance. Furthermore, in the proposed method, a two-degree-of-freedom integral compensation is designed, and hence, the transient response is not deteriorated by the integral action because the integral action is canceled when there is neither modeling nor disturbance. Moreover, in the presence of the modeling error or disturbance, the integral compensation is revealed, and hence, the steady-state error is eliminated on both the intersample and sampled response.

This paper discusses design of Generalized Predictive Control (GPC) scheme. GPC is designed in two cases; the first is a dual-rate (DR) system, where the sampling interval of a plant output is an integer multiple of the holding interval of a control input, and the second is a fast-rate single-rate (FR-SR) system, where both the holding and sampling intervals are equal to the holding interval of the DR system. Furthermore, the relation between them is investigated, and this study gives the conditions that FR-SR and DR GPC become equivalent. To this end, a future reference trajectory of DR GPC is rewritten, and a future predictive output of the FR-SR GPC is rearranged.

We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.