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We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.9 pp.1605-1611

- Publication Date
- 2010/09/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E93.A.1605

- Type of Manuscript
- PAPER

- Category
- VLSI Design Technology and CAD

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

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Takashi SAITO, Toshiki KANAMOTO, Saiko KOBAYASHI, Nobuhiko GOTO, Takao SATO, Hitoshi SUGIHARA, Hiroo MASUDA, "A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 9, pp. 1605-1611, September 2010, doi: 10.1587/transfun.E93.A.1605.

Abstract: We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.1605/_p

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@ARTICLE{e93-a_9_1605,

author={Takashi SAITO, Toshiki KANAMOTO, Saiko KOBAYASHI, Nobuhiko GOTO, Takao SATO, Hitoshi SUGIHARA, Hiroo MASUDA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance},

year={2010},

volume={E93-A},

number={9},

pages={1605-1611},

abstract={We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.},

keywords={},

doi={10.1587/transfun.E93.A.1605},

ISSN={1745-1337},

month={September},}

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TY - JOUR

TI - A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1605

EP - 1611

AU - Takashi SAITO

AU - Toshiki KANAMOTO

AU - Saiko KOBAYASHI

AU - Nobuhiko GOTO

AU - Takao SATO

AU - Hitoshi SUGIHARA

AU - Hiroo MASUDA

PY - 2010

DO - 10.1587/transfun.E93.A.1605

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E93-A

IS - 9

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - September 2010

AB - We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.

ER -