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Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.8 pp.2040-2047

- Publication Date
- 2010/08/01

- Publicized

- Online ISSN
- 1745-1361

- DOI
- 10.1587/transinf.E93.D.2040

- Type of Manuscript
- Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)

- Category
- Logic Design

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Noboru TAKAGI, "A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2040-2047, August 2010, doi: 10.1587/transinf.E93.D.2040.

Abstract: Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2040/_p

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@ARTICLE{e93-d_8_2040,

author={Noboru TAKAGI, },

journal={IEICE TRANSACTIONS on Information},

title={A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations},

year={2010},

volume={E93-D},

number={8},

pages={2040-2047},

abstract={Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.},

keywords={},

doi={10.1587/transinf.E93.D.2040},

ISSN={1745-1361},

month={August},}

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TY - JOUR

TI - A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations

T2 - IEICE TRANSACTIONS on Information

SP - 2040

EP - 2047

AU - Noboru TAKAGI

PY - 2010

DO - 10.1587/transinf.E93.D.2040

JO - IEICE TRANSACTIONS on Information

SN - 1745-1361

VL - E93-D

IS - 8

JA - IEICE TRANSACTIONS on Information

Y1 - August 2010

AB - Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model.

ER -