DC motors are indispensable to improve the automotive functions. Recently, 70-100 motors are installed on luxury cars and this number is increasing year by year. With the recent demand for improved fuel economy and better equipment layout, the improvement of the motor's efficiency and the minimization of the motor size are the key to enhancing the competitive edge of the products. Adopting the high-density coil is an effective method for that, but it is accompanied by the commutation inductance rise which causes the commutation arc increase. The increase of commutation arc decreases motor life, because it causes the rise of brush/commutator wear. This report describes an arc-reducing effect obtained when capacitors are built into a commutation circuit for the purpose of reducing arcing under high commutation inductance conditions. The results of an evaluation using a equivalent commutation circuit and carbon brush/carbon flat-commutator showed that although a commutation circuit with built-in capacitor generated the same arc energy as a commutation circuit without a capacitor above a certain value of residual current, it displayed an excellent arc-reducing effect below that value of residual current.

We achieved first dynamic all-optical signal processing with a bandgap-engineered MZI SOA all-optical switch. The wide-gap Selective Area Growth (SAG) technique was used to provide multi-bandgap materials with a single step epitaxy. The maximum photoluminescence (PL) peak shift obtained between the active region and the passive region was 192 nm. The static current switching with the fabricated switch indicated a large carrier induced refractive index change; up to 14 π phase shift was obtained with 60 mA injection in the SOA. The carrier recovery time of the SOA for obtaining a phase shift of π was estimated to be 250-300 ps. A clear eye pattern was obtained in 2.5 Gbps all-optical wavelength conversion. This is the first all-optical wavelength conversion demonstration with a bandgap-engineered PIC with either selective area growth or quantum-well intermixing techniques.

Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signal and monolithic microwave integrated circuits. The InGaAs/InP DHBTs were grown by MBE and fabricated using conventional process techniques. Devices with an emitter junction area of 4.8 µm2 exhibited peak cutoff frequency (fT) and maximum oscillation frequency (fMAX) values of 265 and 305 GHz, respectively, and a breakdown voltage (BVCEo) of over 5 V. Using this technology, a set of mixed-signal IC building blocks for ≥ 80 Gbit/s fibre optical links, including distributed amplifiers (DA), voltage controlled oscillators (VCO), and multiplexers (MUX), have been successfully fabricated and operated at 80 Gbit/s and beyond.

If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.

A LC oscillator based upon the quadrature magnetic coupling to generate a mutual negative resistance (mu-R) is introduced. The topology offers enhanced optimum phase noise at low supply voltages by enabling extended circuit operation in the current-limited regime through the control of its mutual inductors' coupling factor, k. The principal operation of the mu-R oscillator is described and its comparison with the popular cross-coupled topology is discussed. The capability of the technique is demonstrated via design examples of 1.8 GHz oscillators. Simulations show that, by employing inductors with a self-inductance of 2 nH, a quality factor of about 7.5 and a coupling k=0.52, the mu-R oscillator exhibits the minimum phase noise of -142 dBc/Hz at 3 MHz-offset with 18 mA bias current and 2 V supply. This is 3-dB more than the minimum achievable phase noise in the cross-coupled oscillator with identical component parameters and supply voltage level.

A new method to reduce power consumption of a linear transconductor is proposed in this paper. The minimum tail current for the operation of the transconductor is supplied by a new current source circuit. The proposed circuit is based on a dynamic biasing current technique. Results of SPICE simulation show that the proposed technique is very effective to reduce power consumption of the transconductor.

This paper discusses the design and performance of on-chip passive components of transmission lines (TR) and inductors. First, the measurement technique of on chip passives is discussed. A transmission line that can be used for Gbps signal propagation on Si CMOS is examined. As a high density transmission line structure of diagonal-pair differential TR line is described. Also, a circuit and TR line is introduced for above 10 Gbps signal propagation. The on-chip inductor which is a key passive component in RF application of Si CMOS technology is discussed. We examine some on-chip inductors that have been developed in our group: small area inductor, high performance inductor using WL-CSP (Wafer-Level Chip-Size-Packaging) technology. Finally, a wide tuning range LC-VCO using a variable inductor for RF reconfigurable circuit is introduced.

The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are discussed. For frequency-tunable circuits, a low-voltage MOS varactor tuning technique is presented. The techniques discussed are applied to two different OTA topologies, as well as to an automatically tuned, fifth-order active RC filter. This material is largely based on the work of the authors as described in [1]-[5].

This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.

In this paper, we show the generalized method of the time-domain circuit simulation based on LIM. Our method is applicable to any structure of circuits by combination with the SPICE-like method. In order to show the validity and efficiency of our method, an example circuit is simulated and the proposed method is compared with the conventional ones.

This paper presents a design method of multi-stage, multi-way microstrip power dividers with the aim of constructing a compact low-loss power divider with numbers of outputs. First, an integration design technique of power dividers composed of multi-step, multi-furcation and mitered bends is described. Since the analytical technique is founded on the planar circuit approach combined with the segmentation method, the optimization of the circuit patterns can be performed in a reasonable short computation time. Next, the present method is applied to the design of broadband Nn-way power dividers such as 32-way power divider consisting of 3-way dividers in two-stage structures, respectively. In addition, a 12-way power divider constructed from a series connection of a 3-way and three 4-way dividers is designed. The dividers equivalently contain a 3-section Chebyshev transformer to realize broadband properties. As a result, the fractional bandwidths of nearly 85% and 66.7% for the power-split imbalance less than 0.2 dB and the return loss better than -20 dB are obtained for the 9- and 12-way power dividers, respectively. The validity of these design results is confirmed by a commercial em-simulator (Ansoft HFSS) and experiments.

In this paper, a practical clock-scheduling engine is introduced. The minimum feasible clock-period is obtained by using a modified Bellman-Ford shortest path algorithm. Then an optimum cost clock-schedule is obtained by using a bipartite matching algorithm. It also provides useful information to circuit synthesis tools. The experiment to a circuit with about 10000 registers and 100000 signal paths shows that a result is obtained within a few minutes. The computation time is almost linear to the circuit size in practice.

The analog IC technology, might sound old-fashioned, is still important for the future wireless systems such as 4G cellular phone systems, broadband wireless networkings, and wireless sensor networkings. The analog features and issues of the scaled CMOS transistor, the basic issue and the technology trend for the ADC as an important building block of wires systems, and the feature of the digital RF architecture proposed recently are reviewed and discussed. Higher speed and lower power consumption are expected for low SNR systems along with the further technology scaling. However, the high SNR system is not realized easily due to a decrease of signal voltage. One of the important technology trends is the digitalization of RF signal to realize the system flexibility, robustness, area shrinking, and TAT shortening.

Temperature-tracking is becoming of paramount importance in modern electronic design automation tools. In this paper, we present a deterministic thermal placement algorithm for standard cell based layout which can lead to a smooth temperature distribution over the die. It is mainly based on Fiduccia-Mattheyses partition scheme and a former substrate thermal model that can convert the known temperature constraints into the corresponding power distribution constraints. Moreover, a kind of force-directed heuristic based on cells' power consumption is introduced in the above process. Experimental results demonstrate a comparatively uniform temperature distribution and show a reduction of the maximal temperature on the die.

The Ethernet network is widely used and adopted to the access portion or metro area for the reason of new applications for native Ethernet services or its economical advantage. Apart from these applications for native Ethernet, an encapsulation technology to transport legacy services over Ethernet, i.e. TDM over Ethernet, is focused on. In order to apply it to the carrier networks, it is necessary to meet Quality of Service (QoS) requirements, and the consideration of operation, administration and maintenance (OAM) aspects are indispensable. Furthermore, in order for higher reliability, it is required to apply protection function to the networks. We have studied the encapsulation method of TDM signals applied to circuit emulator accommodating TDM signals over Ethernet. In addition, the OAM mechanism and the protection function are studied. This paper shows the frame format, the detail of the OAM mechanism and the protection function, and introduces a developed circuit for adaptation of TDM over Ethernet.

We have developed a 32-bit, 32-word, and 9-read, 7-write ported register file. This register file has several circuits and techniques for reducing the impact of process variation that is marked in recent process technologies, voltage variation, and temperature variation, so called PVT variation. We describe these circuits and techniques in detail, and confirm their effects by simulation and measurement of the test chip.

This paper describes a novel adaptive clock recovery method that uses proportional-integral-derivative (PID) control. The adaptive clock method is a clock recovery technique that synchronizes connected terminals via packet networks, and will be indispensable for circuit emulation services in the next generation Ethernet. Our adaptive clock method simultaneously achieves a short starting-time, accuracy, stable recovery clock frequency, and few buffer delays using the PID control technique. We explain the numerical simulations, experimental results, and circuit designs.