IEICE TRANSACTIONS on Information
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm
Summary :
If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.
- Publication
- IEICE TRANSACTIONS on Information Vol.E89-D No.7 pp.2301-2305
- Publication Date
- 2006/07/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e89-d.7.2301
- Type of Manuscript
- LETTER
- Category
- VLSI Systems
Authors
Keyword
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Ryoichiro ATONO, Shuichi ICHIKAWA, "Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm" in IEICE TRANSACTIONS on Information,
vol. E89-D, no. 7, pp. 2301-2305, July 2006, doi: 10.1093/ietisy/e89-d.7.2301.
Abstract: If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e89-d.7.2301/_p
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@ARTICLE{e89-d_7_2301,
author={Ryoichiro ATONO, Shuichi ICHIKAWA, },
journal={IEICE TRANSACTIONS on Information},
title={Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm},
year={2006},
volume={E89-D},
number={7},
pages={2301-2305},
abstract={If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.},
keywords={},
doi={10.1093/ietisy/e89-d.7.2301},
ISSN={1745-1361},
month={July},}
Copy
TY - JOUR
TI - Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm
T2 - IEICE TRANSACTIONS on Information
SP - 2301
EP - 2305
AU - Ryoichiro ATONO
AU - Shuichi ICHIKAWA
PY - 2006
DO - 10.1093/ietisy/e89-d.7.2301
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E89-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2006
AB - If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.
ER -
English
