A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications
Summary :
The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.811-813
- Publication Date
- 2006/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.6.811
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit and Device Technologies)
- Category
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Yasuhiro SUGIMOTO, Yuji GOHDA, Shigeto TANAKA, "A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 6, pp. 811-813, June 2006, doi: 10.1093/ietele/e89-c.6.811.
Abstract: The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.811/_p
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@ARTICLE{e89-c_6_811,
author={Yasuhiro SUGIMOTO, Yuji GOHDA, Shigeto TANAKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications},
year={2006},
volume={E89-C},
number={6},
pages={811-813},
abstract={The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.},
keywords={},
doi={10.1093/ietele/e89-c.6.811},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 811
EP - 813
AU - Yasuhiro SUGIMOTO
AU - Yuji GOHDA
AU - Shigeto TANAKA
PY - 2006
DO - 10.1093/ietele/e89-c.6.811
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.
ER -
English
