A CMOS current-mode S-shape correction circuit with shape-adjustable control is proposed for suiting different LCD panel's characteristics from different manufactures. The correction shape is divided into three segments for easy curve-fitting using three lower order polynomials. Each segment could be realized by a corresponding current-mode circuit. The proposed circuit consists of several control points which are designed for tuning the correction shape. The S-shape correction circuit was fabricated using the 0.35 µm TSMC CMOS technology. The measured input dynamic range of the circuit is from 0 µA to 220 µA. The -3 dB bandwidth of the circuit is up to 262 MHz in a high input current region.

In this letter a new active element the Current Follower Transconductance Amplifier (CFTA) for the realization of the current-mode analog blocks is presented. The element is a combination of the Current Follower (CF) and the Balanced Output Transconductance Amplifier (BOTA). Possible internal structure of the CFTA is presented. The usage of the new active element is shown on the design of the Kerwin-Huelsman-Newcomb (KHN) structure working in the current mode. The frequency filter using the CFTA elements has been designed using the signal-flow graphs. The circuit structure employs three CFTA elements and two grounded passive elements. The filter enables realizing not only the basic functions as the low- (LP), band- (BP) and high-pass (HP) but also the notch and all-pass (AP) filter. The advantage of the structure presented is that the outputs of the filter are at high impedance and hence it is not necessary to use other auxiliary active elements. The properties of the filter proposed were verified by sensitivity and AC analyses in the PSPICE program.

In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realizes the full-parallel calculation without any ripple carry propagation. First, the 4-bit addition and multiplication algorithms employing the multiple-valued digit ORNS are optimized through logic-level analyses. In the multiplier, the maximum digit value and the number of modulo operations in series are successfully reduced from 49 to 29 and from 3 to 2, respectively, by the arrangement of addition lines. Next, circuit components such as a current mirror are verified using HSPICE. The proposed switched current mirror which has functions of a current mirror and an analog switch is effective to reduce the minimum operation voltage by about 0.13 volt. Besides an ordinary strong-inversion region, the circuit components operated under the weak-inversion region show good simulation results with the unit current of 10 nanoamperes, and it brings both of the lower power dissipation and the stable operation under the lower supply voltage.

A multiple-valued current-mode (MVCM) circuit using current-flow control is proposed for a power-greedy sequential linear-array system. Whenever operation is completed in processing element (PE) at the present stage, every possible current source in the PE at the previous stage is cut off, which greatly reduces the wasted power dissipation due to steady current flows during standby states. The completion of the operation can be easily detected using "operation monitor" that observes input and output signals at latches, and that generates control signal immediately at the time completed. Since the wires of data and control signals are shared in the proposed MVCM circuit, no additional wires are required for current-flow control. In fact, it is demonstrated that the power consumption of the MVCM circuit using the proposed method is reduced to 53 percent in comparison with that without current-source control.

This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90 nm CMOS technology, at a comparable BER.

A current-mode squarer/divider circuit with a novel translinear cell is presented for automotive applications. The proposed circuit technique increases the accuracy of the squarer/divider function with better input dynamic range and temperature insensitivity. Simulation results show that the variation of the output current is within ±0.2% over the temperature range from -40 to 140.

This paper presents a high-speed 5454-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 µm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8 V supply occupying a 0.85 mm2 active area.

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 µm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

The possibility of realizing a CMOS pipelined current-mode A-D converter (ADC) for video applications has been examined. Two times the input current is obtained at the output of a bit-block of a pipelined ADC by subtracting the negative output current from the positive output current in the pseudo-differential configuration. Subtraction of the sub-DAC (D-to-A converter) current from the two times the input current is performed by controlling of the current comparator, which compares the positive and the negative input currents. A prototype chip has been implemented using 0.35 µm CMOS devices. It operates in 28 MS/s, and showed a 42 dB signal-to-noise ratio from the 2 V supply voltage.

This paper presents the design of new fully differential CMOS class A and class AB current-mode transmitters for multi-Gbps serial links. A high multiplexing speed is achieved by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully complementary operation of the multiplexers and the fully differential configuration of the transmitters minimizes the effect of common-mode disturbances and that of EMI from channels to neighboring devices. Large output current swing is obtained by making use of differential current amplifiers and the differential rail-to-rail configuration. The constant current drawn from the supply voltage minimizes the noise injected into the substrate. The transmitters have been implemented in TSMC's 1.8 V 0.18 µm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V device models. Simulation results confirm that the proposed transmitters are capable of transmitting data at 10 Gbps.

This paper introduces current-mode biquad using multiple current output operational transconductance amplifiers (OTAs) and grounded capacitors. The circuit configuration is obtained from a second-order integrator loop structure with loss-less and lossy integrators. The proposed circuit can realize low-pass, band-pass, high-pass, band-stop and all-pass transfer functions by suitably choosing the input and output terminals. And the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. It is also made clear that the proposed circuit has very low sensitivities with respect to the circuit active and passive elements. An example is given together with simulated results by PSpice.

This paper reviews analog-circuit researches in the 1990's especially from an academic-side point of view with the aim of pursuing what becomes important in the 21st century. To achieve this aim a large number of articles are surveyed and more than 200 are listed in References.

This paper proposes a realization of power factor function generator having an arbitrary base and power factor which are determined by the ratios of the currents provided from outside of the circuit. The circuit characteristics do not depend on any transistor parameters, temperature, and other environmental conditions. The circuit operation is based on current mode that has a capability of low power supply voltage operation below than 2.0 V. SPICE simulation has been carried out using 0.7 µm BiCMOS parameters and shows quite good transfer characteristics.

This paper describes an IC implementation of current-mode chaotic neuron circuit for the chaotic neural network. The chaotic neuron circuit which composes of a first generation switched-current integrator and a conventional current amplifier is fabricated in a standard 0.8 µ m CMOS technology. Experimental results of the chaotic neuron circuit reproduce the dynamical behavior of the chaotic neuron model.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

In this letter, a novel current-mode operational amplifier (COA) is proposed. The proposed COA can operate at 2 V (1 V) supply voltage. For high frequency operation it has only an npn transistor in signal path. Finally, SPICE simulation are shown to verify the performance of the proposed COA.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.