Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic

Jing SHEN; Koichi TANNO; Okihiko ISHIZUKA; Zheng TANG

Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic

Jing SHEN, Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG

Full Text Views

0

Cite this

Summary :

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by V_T (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC^*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.

Publication: IEICE TRANSACTIONS on Information Vol.E82-D No.5 pp.940-948

Publication Date: 1999/05/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)

Category: Circuits

Cite this

Copy

Jing SHEN, Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, "Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic" in IEICE TRANSACTIONS on Information, vol. E82-D, no. 5, pp. 940-948, May 1999, doi: .
Abstract: A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by V_T (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC^*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_5_940/_p

Copy

@ARTICLE{e82-d_5_940,
author={Jing SHEN, Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG, },
journal={IEICE TRANSACTIONS on Information},
title={Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic},
year={1999},
volume={E82-D},
number={5},
pages={940-948},
abstract={A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by V_T (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC^*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.},
keywords={},
doi={},
ISSN={},
month={May},}

Copy

TY - JOUR
TI - Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic
T2 - IEICE TRANSACTIONS on Information
SP - 940
EP - 948
AU - Jing SHEN
AU - Koichi TANNO
AU - Okihiko ISHIZUKA
AU - Zheng TANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 1999
AB - A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by V_T (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC^*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.
ER -