A novel ferroelectric-gate transistor with split-gate structure has been proposed and its read out characteristics have been analyzed. "Transistor-type" FeRAMs have a problem in degradation of readout current, i.e. when the readout voltage is applied at the gate, the current of readout operation is smaller than that of write operation. We demonstrate by SPICE simulation that the proposed split-gate structure ferroelectric-FET can overcome the problem.

A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.

A neuron-MOS transistor (νMOS) is applied to current-mode multi-valued logic (MVL) circuits. First, a novel low-voltage and low-power νMOS current mirror is presented. Then, a threshold detector and a quaternary T-gate using the proposed νMOS current mirrors are proposed. The minimum output voltage of the νMOS current mirror is decreased by VT (threshold voltage), compared with the conventional double cascode current mirror. The νMOS threshold detector is built on a νMOS current comparator originally composed of νMOS current mirrors. It has a high output swing and sharp transfer characteristics. The gradient of the proposed comparator output in the transfer region can be increased 6.3-fold compared with that in the conventional comparator. Along with improved operation of the novel current comparator, the discriminative ability of the proposed νMOS threshold detector is also increased. The performances of the proposed circuits are validated by HSPICE with Motorola 1.5 µm CMOS device parameters. Furthermore, the operation of a νMOS current mirror is also confirmed through experiments on test chips fabricated by VDEC*. The active area of the proposed νMOS current mirror is 63 µm 51 µm.