New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p+/n+ interband tunnel junctions in series between a p+ source and a p+ drain through n+ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p+/n+ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.

Gate-controlled negative differential resistance (NDR) due to interband tunneling has been observed at room temperature in a Surface Tunnel Transistor (STT). The STT consists of a highly degenerate p+-drain, an n+-doped channel with an insulated gate, and an n+-source connected to the channel. To demonstrate application as a functional device, a bistable circuit consisting of only one STT and one load resistor was organized and its operation was confirmed. The obtained valley current in the NDR characteristics of the STT, however, is relatively large and limits the device performance. In order to clarify the origin of the valley current, we fabricated p+-n+ tunnel diodes in which growth interruption was done at the pn junction, and investigated the dependence of the NDR characteristics on both the impurity concentration at the regrown interface and the temperature. These measurements indicate that the valley current is mainly caused by the excess tunneling current through traps formed by the residual oxygen at the regrown interface.

In this paper, we propose a surface-based reconstruction technique which simplifies the process of scene reconstruction and increase reliability. Integrationg grid coding and intensity image analysis methods, discontinuities are classified and stable surfaces which make up the skeleton structure of a room (i.e., wall, ceiling, floor, etc.) are extracted. Local models are then reconstructed under the planar assumption, and merged into the global model. The experimental results show that local errors do not radically alter the adjacency relationships of detected surfaces, so robust reconstruction can be achieved.

A resonant-tunneling-diode (RTD) based sense amplifier circuit design has been proposed for the first time to envision a very high-speed and low-power memory system that also includes refresh-free, compact RTD-based memory cells. By combining RTDs with n-type transistors of conventional complementary metal oxide semiconductor (CMOS) devices, a new quantum MOS (Q-MOS) family of logic circuits, having very low power-delay product and good noise immunity, has recently been developed. This paper introduces the design and analysis of a new QMOS sense amplifier circuit, consisting of a pair of RTDs as pull-up loads in conjunction with n-type pull-down transistors. The proposed QMOS sensing circuit exhibits nearly 20% faster sensing time in comparison to the conventional design of a CMOS sense amplifier. The stability analysis done using phase-plot diagram reveals that the pair of back-to-back connected static QMOS inverters, which forms the core of the sense amplifier, has meta-stable and unstable states which are closely related to the I-V characteristics of the RTDs. The paper also analyzes in details the refresh-free memory cell design, known as tunneling static random access memory (TSRAM). The innovative cell design adds a stack of two RTDs to the conventional one-transistor dynamic RAM (DRAM) cell and thereby the cell can indefinitely hold its charge level without any further periodic refreshing. The analysis indicates that the TSRAM cell can achieve about two orders of magnitude lower stand-by power than a conventional DRAM cell. The paper demonstrates that RTD-based circuits hold high promises and are likely to be the key candidates for the future high-density, high-performance and low-power memory systems.