We introduce a novel neural network called the T-Model and investigates the learning ability of the T-Model neural network. A learning algorithm based on the least mean square (LMS) algorithm is used to train the T-Model and produces a very good result for the T-Model network. We present simulation results on several practical problems to illustrate the efficiency of the learning techniques. As a result, the T-Model network learns successfully, but the Hopfield model fails to and the T-Model learns much more effectively and more quickly than a multi-layer network.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.

A new arithmetic multiple-valued algebra with functional completeness is introduced. The algebra is called Neuro-Algebra for it has very similar formula and architecture to neural networks. Two canonical forms of multiple-valued functions of this Neuro-Algebra are presented. Since the arithmetic operations of the Neuro-Aglebra are basically a weighted-sum and a piecewise linear operations, their implementations are very simple and straightforward. Furthermore, the multiple-valued networks based on the Neuro-Algebra can be trained by the traditional back-propagation learning algorithm directly.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

The analog inverter for realization of the NOT function is the indispensable circuit element in the voltage-mode analog and digital signal processing. In this paper, we propose a novel analog inverter composed of only two neuron-MOS transistors. The analog inverter has the weighted negative feedback mechanism to operate both of neuron-MOS transistors under the saturation region in all input ranges. In verification using HSPICE simulations, the analog inverter performs the high linearity with errors of approximately 40 [mV] in all input ranges, particularly errors of less than 19 [mV] in more than 90% of input ranges. And, the maximum power consumption of the analog inverter is less than 1.5 [µW] although a peak of a standard CMOS inverter is around 30 [µW] under the supply voltage of 3.0 [V]. These good stability and results are produced by the negative feedback. Furthermore, fabrication costs of the analog inverters can be kept at the minimum because neuron-MOS transistors can be actualized in a conventional CMOS process without any additional process. For applications of the analog inverter, the voltage comparator with high noise margins is designed and is applied to the two-input MAX and the two-input MIN circuits in the voltage-mode. The MAX and the MIN circuits for realization of the MAX and the MIN functions, respectively, can be composed of total ten transistors each. They also perform well in verifications. On the basis of the proposed circuits, almost all of voltage-mode multi-valued logic circuits with high-performance can be realized like present binary logic systems. And, the proposed circuits can give full play to the high linearity and advantages for the arbitrary transformation of signal forms in the analog signal processing such as the fuzzy control.

We report on an experimental hysteresis in the Hopfield networks and examine the effect of the hysteresis on some important characteristics of the Hopfield networks. The detail mathematic description of the hysteresis phenomenon in the Hopfield networks is given. It suggests that the hysteresis results from fully–connected interconnection of the Hopfield networks and the hysteresis tends to makes the Hopfield networks difficult to reach the global minimum. This paper presents a T–Model network approach to overcoming the hysteresis phenomenon by employing a half–connected interconnection. As a result, there is no hysteresis phenomenon found in the T–Model networks. Theoretical analysis of the T–Model networks is also given. The hysteresis phenomenon in the Hopfield and the T–Model networks is illustrated through experiments and simulations. The experiments agree with the theoretical analysis very well.

We introduce a novel neural network with a trigonometric interconnection called the T-Model neural network in this paper. A VLSI implementation of the T-Model neural network based on CMOS current-mode circuits is also presented. The circuit is completely compatible with standard VLSI technology. A set of neuron-type elements of CMOS current-mode circuits is described and a very large scale neural network is also synthesized. The feasibility and the operation principle of the synthesis of the T-Model neural network using CMOS current-mode circuits are demonstrated and confirmed by experimental results of fabricated CMOS VLSI neural chips.

In this paper, a threshold voltage (VT) cancellation circuit for neuron-MOS (νMOS) analog circuits is described. By connecting the output terminal of this circuit with one of the input terminals of the νMOS transistor, cancellation ofVT is realized. The circuit has advantages of ground-referenced output and is insensitive to the fluctuation of bias and supply voltages. Second-order effects, such as the channel length modulation effect, the mobility reduction effect and device mismatch of the proposed circuit are analyzed in detail. Low-power and high-swing νMOS cascode current mirror is presented as an application. Performance of the proposed circuits is confirmed by HSPICE simulation with MOSIS 2. 0 µ p-well double-poly and double-metal CMOS device parameters.

In this paper, we propose a learning fuzzy network (LFN) which can be used to implement most of fuzzy logic functions and is much available for hardware implementations. A learning algorithm largely borrowed from back propagation algorithm is introduced and used to train the LFN systems for several typical fuzzy logic problems. We also demonstrate the availability of the LFN hardware implementations by realizing them with CMOS current-mode circuits and the capability of the LFN systems by testing them on a benchmark problem in intelligent control-the inverted pendulum system. Simulations show that a learning fuzzy network can be realized with the proposed LFN system, learning algorithm, and hardware implementations.

In this paper, a virtual-short circuit which consists of only two MOS transistors operated in the weak-inversion region is proposed. It has the advantages of almost zero power consumption, low voltage operation, small chip area, and no needlessness of bias voltages or currents. The second order effects, such as the device mismatch, the Early effect, and the temperature dependency of the circuit are analyzed in detail. Next, current-controlled and voltage-controlled current sources using the proposed virtual-short circuit are presented as applications. The performance of the proposed circuits is estimated using SPICE simulation with MOSIS 1. 2 µm CMOS device parameters. The results are reported on this paper.

A model for a large network with an unidirectional linear respone (ULR) is proposed in this letter. This deterministic system has powerful computing properties in very close correspondence with earlier stochastic model based on McCulloch-Pitts neurons and graded neuron model based on sigmoid input-output relation. The exclusive OR problems and other digital computation properties of the earlier models also are present in the ULR model. Furthermore, many analog and continuous signal processing can also be performed using the simple ULR neural network. Several examples of the ULR neural networks for analog and continuous signal processing are presented and show extemely promising results in terms of performance, density and potential for analog and continuous signal processing. An algorithm for the ULR neural network is also developed and used to train the ULR network for many digital and analog as well as continuous problems successfully.

A novel comparator-based switched-capacitor voltage-to-frequency converter is presented. By using the op-amp as the comparator, it can be operated over wide frequency range. Conversion sensitivity is also insensitive to capacitance ratio and parasitic capacitances between each node and ground.

A direct gradient descent learning algorithm of energy function in Hopfield neural networks is proposed. The gradient descent learning is not performed on usual error functions, but the Hopfield energy functions directly. We demonstrate the algorithm by testing it on an analog-to-digital conversion and an associative memory problems.

This paper describes an MOS charge-mode version of a T-Model neural-based PCM encoder. The neural-based PCM encoding networks are designed, simulated and implemented using MOS charge-mode circuits. Simulation results are given for both the T-Model and the Hopfield model CMOS charge-mode PCM encoders, and demonstrate the T-Model neural-based one performs the PCM encoding perfectly, while the Hopfield one fails to.

This paper presents an optimum design method of reliable networks. This paper, first, discusses several design methods for undirected graphs. It is shown that one new method of them gives graphs with the minimum diameter in a certain domain. In order to obtain optimum graph when the number of nodes and degree are given, this paper next discusses a method to obtain modified graphs with larger connectivity and also with the minimum diameter from known graphs which have diameter 1 over the minimum.

A novel buffer-based switched-capacitor (SC) integrator integrable by a method of reducing capacitance ratio is presented. By this method, high Q sc filter can be made by realizable capacitance ratio on CMOS process. The proposed integrator can also be operated over wide frequency range because it uses a unity gain buffer (UGB).

In this letter, we demonstrate an experimental CMOS neural circuit towards an understanding of how particular computations can be performed by a T-Model neural network. The architecture and a digital hardware implementation of the learning T-Model network are presented. Our experimental results show that the T-Model allows immense collective network computations and powerful learning.

This paper extends an earlier study on the T-Model neural network to its collective computational properties. We present arguments that it is necessary to use the half-interconnected T-Model networks rather than the fully-interconnected Hopfield model networks. The T-Model has been generated in response to a number of observed weaknesses in the Hopfield model. This paper identities these problems and show how the T-Model overcomes them. The T-Model network is essentially a feedforward network which does not produce a local minimum for computations. A concept for understanding the dynamics of the T-Model neural circuit is presented and its performance is also compared with the Hopfield model. The T-Model neural circuit is implemented and tested with standard CMOS technology. Simulations and experiments show that the T-Model allows immense collective network computations and does not produce a local minimum. High densities comparable to that of the Hopfield model implementations have also been achieved.

In this letter, a linear variable resistor circuit using an FG-MOSFET (floating-gate MOSFET) is proposed. This is based on Schlarmann's variable resistor and is very simple. The advantage of the proposed circuit is a wide-input range. The utility of the proposed circuit was confirmed by HSPICE simulation with 1.2 µm CMOS process parameters. The simulation results are reported in this letter.