A 1-V, 1-V_p-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors

Koichi TANNO, Okihiko ISHIZUKA, Zheng TANG

Summary :

In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0 µm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and 3 dB bandwidth are 9.56 µW and 107 MHz, respectively. The active area of the proposed multiplier is 210 µm 140 µm.

• Publication: IEICE TRANSACTIONS on Electronics Vol.E82-C No.5 pp.750-757
• Publication Date: 1999/05/25
• Type of Manuscript: PAPER
• Category: Electronic Circuits

Authors

Koichi TANNO
Okihiko ISHIZUKA
Zheng TANG

Keyword

multiplier,  low voltage,  low power,  neuron MOS transistor,  analog integrated circuit