This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

A fully integrated 16-phase 8-branch Dickson charge pump is proposed and implemented to decrease the power dissipation due to parasitic capacitance at the bottom plate of the boost capacitor. By using the charge recycling concept, 87% of the power consumption related to parasitic capacitance is saved. In a 4-stage version of this charge pump, a maximum power efficiency of 41% is achieved at 35µA output current and 11V output voltage from a 3.3V supply voltage. The proposed multi-branch charge pump can also reach a very low output voltage ripple of only 0.146% at a load resistance of 1MΩ, which is attributed to the fact that the 8-branch charge pump can transfer charges to the output node eight times consecutively during one clock period. In addition, a high voltage gain of 4.6 is achieved in the 4-stage charge pump at light load conditions. The total chip area is 0.57mm2 in a 0.35µm HV CMOS technology.

In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when VDD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.

In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/ under the condition that the temperature range is from -40 to 125 and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Capability of SOTB to effectively reduce leakage by body biasing is fully exploited in BBS. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

Process and temperature variations have become a serious concern for ultra-low voltage (ULV) technology. The clock generator is the essential component for the ULV very-large-scale integration (VLSI). MOSFETs that are operated in the sub-threshold region are widely applied for ULV technology. However, MOSFETs at subthreshold region have relatively high variations with process and temperature. In this paper, process and temperature variations on the clock generators have been studied. This paper presents an ultra-low voltage 2.4GHz CMOS voltage controlled oscillator with temperature and process compensation. A new all-digital auto compensated mechanism to reduce process and temperature variation without any laser trimming is proposed. With the compensated circuit, the VCO frequency-drift is 16.6 times the improvements of the uncompensated one as temperature changes. Furthermore, it also provides low jitter performance.

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.

In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm2). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (VDD =0.52 V), the ADPLL only dissipates 269.9 μW at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of -57.3 dBc with the period jitter of 0.217% UI.

This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5MF (MF = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm2. In near-threshold region (VDD = 0.36 V), the proposed ADPLL only dissipates 68.2 µW and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V VDD operation, the proposed ADPLL dissipates 404.2 µW at 400 MHz. The fast lock-in time of 4.489 µs and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.

A scalable low voltage signaling (SLVS) transmitter, with asymmetric impedance calibration, is proposed for mobile applications which require low power consumption. The voltage swing of the proposed SLVS transmitter is scalable from 40,mV to 440,mV. The proposed asymmetric impedance calibration asymmetrically controls the pull-up and pull-down drivers for the SLVS transmitter with an impedance of 50,$Omega$. This makes it possible to remove the additional regulator used to calibrate the impedance of an output driver by controlling the swing level of a pre-driver. It also maintains the common mode voltage at the center voltage level of the transmitted signal. The proposed SVLS transmitter is implemented using a 0.18-$mu $m 1-poly 6-metal CMOS process with a 1.2-V supply. The active area and power consumption of the transmitter are $250 imes 123 mu$ m$^{2}$ and 2.9,mW/Gb/s, respectively.

Extremely low voltage operation near or below threshold voltage is a key circuit technology to improve the energy efficiency of information systems and to realize ultra-low power sensor nodes. However, it is difficult to operate conventional analog circuits based on amplifier at low voltage. Furthermore, PVT (Process, Voltage and Temperature) variation and random Vth variation degrade the minimum operation voltage and the energy efficiency in both digital and analog circuits. In this paper, extremely low power analog circuits based on comparator and switched capacitor as well as extremely low power digital circuits are presented. Many kinds of circuit technologies are applied to cope with the variation problem. Finally, image processing SoC that integrates digital and analog circuits is presented, where improvement of total performance by a cooperation of analog circuits and digital circuits is demonstrated.

The influence of the splitter plates on the high-current arc roots formation in low voltage circuit breaker is investigated. One arc quenching chamber model is designed, where the shape of the splitter plates can be changed. The capacitor bank circuit is used to provide the test power supply, and the effective value of the prospective short circuit current is fixed to 10kA. High speed CCD camera is adopted to record the arc images during the arcing duration. Arc current and voltage are also measured to analyze the arc characteristics. In addition, a simplified 1-D thermal-electric model is developed to investigate the influence of the splitter plates on the distribution of the current density of the arc plasma with the assumption of local thermal equilibrium (LTE). It shows that the distance between the arc initial ignition location and the splitter plates is crucial to the arc root formation.

In this paper we show that self synchronous circuits can provide robust operation in both soft error prone and low voltage operating environments. Self synchronous circuits are shown to be self checking, where a soft error will either cause a detectable error or halt operation of the circuit. A watchdog circuit is proposed to autonomously detect dual-rail '11' errors and prevent propagation, with measurements in 65 nm CMOS showing seamless operation from 1.6 V to 0.37 V. Compared to a system without the watchdog circuit size and energy-per-operation is increased 6.9% and 16% respectively, while error tolerance to noise is improved 83% and 40% at 1.2 V and 0.4 V respectively. A circuit that uses the dual-pipeline circuit style as redundancy against permanent faults is also presented and 40 nm CMOS measurement results shows correct operation with throughput of 1.2 GHz and 810 MHz at 1.1 V before and after disabling a faulty pipeline stage respectively.

As an application of low electric field to biomedical engineering, this paper attempts to study the dose-effect of biological effects caused by msPEF with experiments on HeLa cells. MTT assay was used to trace the cell electroporation and examine cell viability. It is observed that with the increasing electric field intensity and pulse numbers, IRE effects will occur successively.

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0 V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7 V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400 mV.

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closed-loop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/, current consumption of 14 µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 µm CMOS process.

A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.