IEICE TRANSACTIONS on Fundamentals
Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers
Summary :
In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/℃ under the condition that the temperature range is from -40℃ to 125℃ and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.5 pp.748-754
- Publication Date
- 2018/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.748
- Type of Manuscript
- PAPER
- Category
- Analog Signal Processing
Authors
Kenya KONDO
University of Miyazaki
Koichi TANNO
University of Miyazaki
Hiroki TAMURA
University of Miyazaki
Shigetoshi NAKATAKE
University of Kitakyushu
Keyword
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Kenya KONDO, Koichi TANNO, Hiroki TAMURA, Shigetoshi NAKATAKE, "Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 5, pp. 748-754, May 2018, doi: 10.1587/transfun.E101.A.748.
Abstract: In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/℃ under the condition that the temperature range is from -40℃ to 125℃ and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.748/_p
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@ARTICLE{e101-a_5_748,
author={Kenya KONDO, Koichi TANNO, Hiroki TAMURA, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers},
year={2018},
volume={E101-A},
number={5},
pages={748-754},
abstract={In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/℃ under the condition that the temperature range is from -40℃ to 125℃ and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.},
keywords={},
doi={10.1587/transfun.E101.A.748},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 748
EP - 754
AU - Kenya KONDO
AU - Koichi TANNO
AU - Hiroki TAMURA
AU - Shigetoshi NAKATAKE
PY - 2018
DO - 10.1587/transfun.E101.A.748
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2018
AB - In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/℃ under the condition that the temperature range is from -40℃ to 125℃ and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.
ER -
English
