In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when VDD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/ under the condition that the temperature range is from -40 to 125 and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/°C.

A CMOS bandgap reference circuit without resistors, which can successfully operate under 1V supply voltage is proposed. The improvement is realized by the technique of the voltage divider and a new current source. The most attractive merit is that the proposed circuit breaks the bottleneck of low supply voltage design caused by the constant bandgap voltage value (1.25V). Moreover, the temperature coefficient of the reference voltage Vref is improved by compensating the temperature dependence caused by the current source. The simulation results using a standard CMOS 0.18 um process show that the value of Vref can be achieved around 0.5 V with a minimum supply voltage of 0.85 V. Meanwhile, the temperature coefficient of the output voltage is only 3.5ppm/°C from 0 °C to 70 °C.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

In this paper, a novel 800 mV beta-multiplier reference current source circuit is presented. In order to cope with the narrow input common-mode range of the Opamp in the reference circuit, the resistive voltage divider was employed. High gain Opamp was designed to compensate for the intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18 µm CMOS process with nominal Vth of 420 mV and -450 mV for n-MOS and p-MOS transistor, respectively. The total power consumption including Opamp is less than 50 µW.

A novel design for temperature-compensated complementary metal-oxide semiconductor (CMOS) voltage reference sources by using the 1st order voltage reference taking into account the electrical property of the conventional current generator was proposed to minimize a temperature coefficient. A temperature coefficient of the proposed voltage reference source was estimated by using the current generator, which operated at smaller or larger temperature in comparison with the optimized operating temperature. The temperature coefficient at temperature range between -40 and 125, obtained from the simulated data by using hynix 0.35 µm CMOS technology, was 3.33 ppm/. The simulated results indicate that the proposed temperature-compensated CMOS voltage reference sources by using the 1st order voltage reference taking into account the electrical properties of the conventional current generator can be used to decrease the temperature coefficient.

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 µm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/ for the -20 to +80 temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.

This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25 V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional VBE (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified VT (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25 V is required, the voltage gain of the amplifier for VBE becomes less than one, and the voltage gain of the amplifier for VT becomes small. This enables the size of bipolar transistors for VT generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-µm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of 46 ppm/ over 130 change, a line regulation of 2.2 mV/V for the 0.5 V reference voltage with 8.7 µA of current consumption in the voltage reference part, and a 6% change over 130 change for the 13 µA current source.

A new sub-1-V CMOS bandgap voltage reference without using low-threshold-voltage device is presented in this paper. The new proposed sub-1-V bandgap reference with startup circuit has been successfully verified in a standard 0.25-µm CMOS process, where the occupied silicon area is only 177 µm106 µm. The experimental results have shown that, with the minimum supply voltage of 0.85 V, the output reference voltage is 238.2 mV at room temperature, and the temperature coefficient is 58.1 ppm/ from -10 to 120 without laser trimming. Under the supply voltage of 0.85 V, the average power supply rejection ratio (PSRR) is -33.2 dB at 10 kHz.

A pure CMOS threshold-voltage reference (VTR) circuit achieves temperature (T) coefficient of 5 µV/(T = -60+100) and supply voltage (VDD) sensitivity of 0.1 mV/V (VDD = 35 V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant VTR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm2 in the TEG (Test Element Group) chip fabricated by 1.2 µm n-well CMOS process.

A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-µm CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94 ppm/ over the temperature range from -100 to 150 at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.

A switched capacitor DC-DC voltage converter that has an arbitrary conversion ratio of rational number is presented. A given voltage conversion ratio is systematically expanded to construct a switched capacitor circuit that operates with a two-phase switching clock. The conversion ratio is completely free from capacitance values and ratios under the assumption that there is no charge transfer between the two switching phases. This means that the converter cannot supply any power to the load. This restricts the application of the converters to a very limited area such as a voltage reference generator that only provides a reference voltage and no power to a circuit. The conditions for the convergence of the output voltage and the stray capacitor effects are discussed. The output voltage error and required switching frequency are also discussed when the converter is used as a DC voltage supply source that provides power to a load.

Temperature dependence of drain current is analyzed in detail in terms of mobility and threshold voltage. From the analyses, it is proved that a point exists that the drain current is fixed without depending on temperature when the MOSFET operates in strong inversion. Applying this characteristic, a CMOS temperature-voltage converter operating in strong inversion with high linearity is proposed. SPICE simulation and experimental results are shown, and the corresponding performances are discussed.

A low-voltage silicon-on-insulator (SOI) voltage-reference circuit has been developed. It is based on threshold-voltage-summation architecture and the output is not affected by the input offset of the feedback amplifier. Thus, the output dispersion is considerably reduced. An undoped MOSFET is used as a depletion-mode transistor because of its small threshold voltage. The temperature dependence of normal and undoped MOSFETs in fully depleted CMOS/SOI technology is studied for designing a temperature-insensitive voltage-reference circuit. A prototype circuit, fabricated on a fully depleted CMOS/SIMOX process, has a measured reference voltage of 530 16.8 mV (3σ), and can operate at a supply voltage as low as 0.6 V. The measured temperature coefficient is 0.02 0.06 mV/ (3σ).

A technique to realize a transconductance which is relatively insensitive over temperature variations is reported. Simulation results with MOS and bipolar transistors indicate substantial improvement in temperature insensitivity over a range exceeding 100 degrees Celsius. It should find useful applications in analog LSI/VLSI systems operating over a wide range of temperature.

Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.