In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

This paper proposes a novel approach for implementing an ultra-low-power voltage reference using the structure of self-cascode MOSFET, operating in the subthreshold region with a self-biased body effect. The difference between the two gate-source voltages in the structure enables the voltage reference circuit to produce a low output voltage below the threshold voltage. The circuit is designed with only MOSFETs and fabricated in standard 0.18-µm CMOS technology. Measurements show that the reference voltage is about 107.5 mV, and the temperature coefficient is about 40 ppm/, at a range from -20 to 80. The voltage line sensitivity is 0.017%/V. The minimum supply voltage is 0.85 V, and the supply current is approximately 24 nA at 80. The occupied chip area is around 0.028 mm2.

An area efficiency hybrid decoupling scheme is proposed to suppress the charge pump noise during F-N tunneling program in non-volatile memory (NVM). The proposed scheme is focused on suppressing the average noise power in frequency domain aspect, which is more suitable for the program error reduction in NVMs. The concept of active capacitor is utilized. Feed forward effect of the amplifier is firstly considered in the impedance analysis, and a trade-off relation between in-band and out-band frequency noise decoupling performance is shown. A fast optimization based on average noise power is made to achieve minimum error in the F-N tunneling program. Simulation results show very stable output voltage in different load conditions, the average ripple voltage is 17 mV with up to 20 dB noise-suppression-ratio (NSR), and the F-N tunneling program error is less than 5 mV for a 800 µs program pulse. A test chip is also fabricated in 0.18 µm technology. The area overhead of the proposed scheme is 2%. The measurement results show 24.4 mV average ripple voltage compared to 72.3 mV of the conventional one with the same decoupling capacitance size, while the noise power suppression achieves 15.4 dB.