IEICE TRANSACTIONS on Fundamentals
An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme
Summary :
In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.2 pp.439-446
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.439
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Mengshu HUANG, Yimeng ZHANG, Tsutomu YOSHIHARA, "An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 2, pp. 439-446, February 2012, doi: 10.1587/transfun.E95.A.439.
Abstract: In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.439/_p
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@ARTICLE{e95-a_2_439,
author={Mengshu HUANG, Yimeng ZHANG, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme},
year={2012},
volume={E95-A},
number={2},
pages={439-446},
abstract={In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.},
keywords={},
doi={10.1587/transfun.E95.A.439},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - An Efficient Dual Charge Pump Circuit Using Charge Sharing Clock Scheme
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 439
EP - 446
AU - Mengshu HUANG
AU - Yimeng ZHANG
AU - Tsutomu YOSHIHARA
PY - 2012
DO - 10.1587/transfun.E95.A.439
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2012
AB - In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.
ER -
English
