Direct-current biased optical orthogonal frequency division multiplexing (DCO-OFDM) converts bipolar OFDM signals into unipolar non-negative signals by introducing a high DC bias, which satisfies the requirement that the signal transmitted by intensity modulated/direct detection (IM/DD) must be positive. However, the high DC bias results in low power efficiency of DCO-OFDM. An adaptively biased optical OFDM was proposed, which could be designed with different biases according to the signal amplitude to improve power efficiency in this letter. The adaptive bias does not need to be taken off deliberately at the receiver, and the interference caused by the adaptive bias will only be placed on the reserved subcarriers, which will not affect the effective information. Moreover, the proposed OFDM uses Hartley transform instead of Fourier transform used in conventional optical OFDM, which makes this OFDM have low computational complexity and high spectral efficiency. The simulation results show that the normalized optical bit energy to noise power ratio (Eb(opt)/N0) required by the proposed OFDM at the bit error rate (BER) of 10-3 is, on average, 7.5 dB and 3.4 dB lower than that of DCO-OFDM and superimposed asymmetrically clipped optical OFDM (ACO-OFDM), respectively.

With the rapid increase in the amount of data communication in 5G networks, there is a strong demand to reduce the power of the entire network, so the use of highly power-efficient millimeter-wave (mm-wave) networks is being considered. However, while mm-wave communication has high power efficiency, it has strong straightness, so it is difficult to secure stable communication in an environment with blocking. Especially when considering use cases such as autonomous driving, continuous communication is required when transmitting streaming data such as moving images taken by vehicles, it is necessary to compensate the blocking problem. For this reason, the authors examined an optimum radio access technology (RAT) selection scheme which selects mm-wave communication when mm-wave can be used and select wide-area macro-communication when mm-wave may be blocked. In addition, the authors implemented the scheme on a prototype device and conducted field tests and confirmed that mm-wave communication and macro communication were switched at an appropriate timing.

Many deep convolutional neural network (CNN) inference accelerators on the field-programmable gate array (FPGA) platform have been widely adopted due to their low power consumption and high performance. In this paper, we develop the following to improve performance and power efficiency. First, we use a high bandwidth memory (HBM) to expand the bandwidth of data transmission between the off-chip memory and the accelerator. Second, a fully-pipelined manner, which consists of pipelined inter-layer computation and a pipelined computation engine, is implemented to decrease idle time among layers. Third, a multi-core architecture with shared-dual buffers is designed to reduce off-chip memory access and maximize the throughput. We designed the proposed accelerator on the Xilinx Alveo U280 platform with in-depth Verilog HDL instead of high-level synthesis as the previous works and explored the VGG-16 model to verify the system during our experiment. With a similar accelerator architecture, the experimental results demonstrate that the memory bandwidth of HBM is 13.2× better than DDR4. Compared with other accelerators in terms of throughput, our accelerator is 1.9×/1.65×/11.9× better than FPGA+HBM2 based/low batch size (4) GPGPU/low batch size (4) CPU. Compared with the previous DDR+FPGA/DDR+GPGPU/DDR+CPU based accelerators in terms of power efficiency, our proposed system provides 1.4-1.7×/1.7-12.6×/6.6-37.1× improvement with the large-scale CNN model.

This paper presents a high power efficient pulse VCO with tail-filter for the chip-scale atomic clock (CSAC) application. The stringent power and clock stability specifications of next-generation CSAC demand a VCO with ultra-low power consumption and low phase noise. The proposed VCO architecture aims for the high power efficiency, while further reducing the phase noise using tail filtering technique. The VCO has been implemented in a standard 45nm SOI technology for validation. At an oscillation frequency of 5.0GHz, the proposed VCO achieves a phase noise of -120dBc/Hz at 1MHz offset, while consuming 1.35mW. This translates into an FoM of -191dBc/Hz.

Computer systems with GPUs are expected to become a strong methodology for high-speed encryption processing. Moreover, power consumption has remained a primary deterrent for such processing on devices of all sizes. However, GPU vendors are currently announcing their future roadmaps of GPU architecture development: Nvidia Corp. promotes the Kepler architecture and AMD Corp. emphasizes the GCN architecture. Therefore, we evaluated throughput and power efficiency of three 128-bit block ciphers on GPUs with recent Nvidia Kepler and AMD GCN architectures. From our experiments, whereas the throughput and per-watt throughput of AES-128 on Radeon HD 7970 (2048 cores) with GCN architecture are 205.0Gbps and 1.3Gbps/Watt respectively, those on Geforce GTX 680 (1536 cores) with Kepler architecture are, respectively, 63.9Gbps and 0.43Gbps/W; an approximately 3.2 times throughput difference occurs between AES-128 on the two GPUs. Next, we investigate the reasons for the throughput difference using our micro-benchmark suites. According to the results, we speculate that to ameliorate Kepler GPUs as co-processor of block ciphers, the arithmetic and logical instructions must be improved in terms of software and hardware.

This letter investigates the relationship between antenna position and data communication performance in a magnetic resonance wireless power transfer (MRWPT) system. In MRWPT information such as the types of equipments, the required amount of electrical power, or the timing of power transfer should be exchanged. It is assumed here that power transfer coils in the MRWPT system are employed as antennas for data communication. The frequency characteristics of the antennas change due to coil displacements. The power transfer coils are modeled as a band pass filter (BPF) and the frequency characteristics of the filter are presented in this letter. The characteristics of the filter are derived through circuit simulation and resulting data communication performance is evaluated. Numerical results obtained through computer simulation show that the bit error late (BER) performance can be improved by controlling the center frequency of the communication link.

In this paper, the charge pump efficiency is discussed, and a dual charge pump circuit with complementary architecture using charge sharing clock scheme is presented. The proposed charge sharing clock generator is able to recover the charge from parasitic-capacitor charging and discharging, so that the dynamic power loss in the pumping process is reduced by a half. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the dual charge pump to achieve the between-branch charge sharing. A test chip is fabricated in 0.18 µm process, and the area penalty of the proposed charge sharing clock generator is 1%. From the measurement results, the proposed charge pump shows an overall power efficiency increase with a peak value of 63.7% comparing to 52.3% of a conventional single charge pump without charge sharing, and the proposed clock scheme shows no degradation on the driving capability while the output ripple voltage is reduced by 43%.

The envelope pulse-width modulation (EPWM) transmitter has been proposed to address the power efficiency issue in the linear amplification of multicarrier signals. However, the delta-sigma (Δ-Σ) modulator in the EPWM transmitter generates quantization noise that degrades the output signal quality. In this paper, noise and distortion characteristics of the EPWM transmitter in the amplification of the OFDM signal are presented. First, quantization noise and distortion due to amplitude clipping are analyzed. Theoretical noise power spectral density (PSD) and error vector magnitude (EVM) are obtained as functions of the Δ-Σ modulator and input signal parameters. Then, simulations to validate the noise and distortion characteristics are done using the IEEE 802.11a OFDM signal and first- and second-order Δ-Σ modulators. The effects of bandpass filtering on EVM and adjacent channel leakage power ratio (ACLR) are also obtained by simulation. Results showed good agreement with the analytical results despite the use of the linear-approximation gain plus noise model. The EPWM transmitter that employed the first-order Δ-Σ modulator with a 0.1% clipping probability, an oversampling ratio of 32 and a three-pole Butterworth bandpass filter yielded an EVM of 1.8% and an ACLR of -37.9 dB, which are sufficiently lower than the OFDM transmitter specification.

The medical body area network (MBAN) is an emerging technology to resolve the small area connection issues around human body, especially for the medical applications. This paper proposes a dynamic TDMA (DTDMA) protocol for MBAN with focus on the dependability and power efficiency. In DTDMA, the slots are allocated by the MBAN coordinator only to the devices which have buffered packets and released to other devices after the current allocation. Through the adaptive allocation of the slots in a DTDMA frame, the MBAN coordinator adjusts the duty cycle adaptively with the traffic load. Comparing with the IEEE 802.15.4 MAC protocol, the DTDMA provides more dependability in terms of lower packet dropping rate and less energy consumption especially for an end device of a MBAN.

In this paper, we propose a novel energy-efficient route-discovery scheme with transmission power control (TPC) for ad hoc networks. The proposed scheme is very simple and improves energy efficiency without any information about neighbor nodes. In the proposed scheme, when a node receives a route request (RREQ), the node calculates the routing-level backoff time as being inversely proportional to the received power of the RREQ. After the route discovery, source and intermediate nodes transmit packets by the power-controlled medium access control (MAC) protocol. In addition, we propose an extended version of the proposed scheme for discrete power control devices. Simulation results demonstrate the proposed schemes can discover more energy efficient routes than the conventional schemes.

A power-efficient Dickson-based charge pump circuit is proposed and verified in this paper. Using a PMOS transfer switch in the new circuit solves the problem of the output voltage loss and its body control switch can suppress the parasitic bipolar action. Comparing this new one with the conventional circuit, the new circuit generates output voltage as high as 2.9 VDD while the conventional one only 2 VDD. For their efficiency values, the new circuit has better efficiency than the conventional one by as much as 14.5% with the area overhead of 12.2% using 3.5-µm and 40-V CMOS high-voltage process.

An entire dual-mode transceiver capable of both the conventional GFSK-modulated Bluetooth and the Medium-Rate π/4-DQPSK-modulated Bluetooth has been investigated and reported. The transmitter introduces a novel two-point-modulated polar-loop technique without the global feedback to realize reduced power consumption, small chip area and also high modulation accuracy. The receiver shares all the circuits for both operating modes except the demodulators and also features a newly-proposed cancellation technique of the carrier-frequency offset. The transceiver has been confirmed by system or circuit simulations to meet all the dual-mode Bluetooth specifications. The simulation results show that the transmitting power can be larger than 10 dBm while achieving the total power efficiency above 30% and also RMS DEVM of 0.050. It was also confirmed by simulation that the receiver is expected to attain the sensitivity of -85 dBm in both modes while satisfying the image-rejection and the blocker-suppression specifications. The proposed transceiver will provide a low-cost, low-power single-chip RF-IC solution for the next-generation Bluetooth communication.

In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.

In this paper, we compare two signal designs for uplink quasi-synchronous code division multiple access (CDMA) channels in order to optimize the trade-off between bandwidth efficiency and power efficiency. The design we call band-limited DS/CDMA design, is based on the time-domain assignment of Gold sequences, just as in the ordinary DS/CDMA, but with band-constrained cyclic chip interpolation functions, which is unlike the ordinary DS/CDMA. The other design, MC/CDMA design, is based on frequency-domain assignment of the sequences, as in the ordinary MC/CDMA. In both designs, we assume insertion of guard intervals at the transmitter and frequency-domain processing in reception. Assuming quasi-synchronous arrival of CDMA signals at the CDMA base station and FFT in the effective symbol interval, the intersymbol interference is evaded in both designs. First we identified the signal parameters that optimize bandwidth efficiency in each of the band-limited DS design and MC design. Second, we clarified the signal parameters that optimize the power efficiency as functions of frequency efficiency in each of the two designs. Finally, we derived and compared the trade-off between the bandwidth efficiency and power efficiency of band-limited DS and MC designs. We found a superiority of band-limited DS design over MC design with respect to the optimized trade-off.

Recently, major services provided by mobile communications systems are shifting from voice conversations to data communications over the Internet. There is a strong demand for increasing the data transmission rate. However, an important problem arises; larger peak transmit power is required as transmission rate becomes higher. In this paper, we propose a wireless multi-hop virtual cellular concept to avoid this power problem. The virtual cellular network consists of a central port, which is a gateway to the network, and many distributed wireless ports. Transmit power and frequency efficiencies of the virtual cellular network are evaluated by computer simulation to compare with that of the present cellular networks. In the wireless multi-hop virtual cellular network, routing among wireless ports is an important technical issue. We propose a routing algorithm based on the total uplink transmit power minimization criterion and evaluate the total transmit power by computer simulation.

This paper introduces a power-efficient on-chip DC-DC converter, which produces a 1.0 V output by being stepped-down from a 3.6 V input, utilizes a 10 µH external inductor, and realizes more than 80% power-efficiency. In order to realize a 1.0 V output without decreasing power-efficiency, a synchronous-type rectifier scheme with a reverse current protection circuit is adopted and a reference voltage of less than 1.0 V is developed. The external inductor value is reduced by applying the PWM control scheme and a new low-power 1 MHz triangular waveform oscillator. High-value resistors are used in analog circuits including a voltage reference, a triangular waveform oscillator, an error amplifier, and a comparator to have the ultra-low power characteristics. A chip is actually designed and fabricated by using the 2 µm CMOS process. As a result, a 1 MHz, synchronous, step-down from 3.6 V to 1 V, PWM DC-DC converter has been realized with a power efficiency of more than 80% in the output current range from 40 to 70 mA.

In this paper, a new full on-chip high efficiency DC-DC voltage up converter with no inductance element is presented with power efficiency more than 74%. A method in the charge pump is described to have a regulated 3.3 V from 1.5 V for output power 4 mW. For medium power class, 100-200 mW, a boost converter is designed with on-chip inductor for 1.5 V to 3.3 V conversion. A buck converter is also designed for 3.3 V to 1 V conversion with power efficiency 72%. Inductor property of bond-wire is employed in the on-chip inductors. Analysis of efficiency relations and simulation results are presented for 0.35 µm CMOS technology.

A new modulation technique for "LInear modulation with Nonlinear Translation" (LINT) is proposed. The new LINT technique is an extension of the popular LINC (LInear amplification with Nonlinear Components) technique for power efficient transmitter operation with spectrally efficient linear modulations. While providing this advantage, the LINT technique also incorporates the principles of direct modulation and provides frequency translation without the use of multiple stages of bulky upconversion circuitry. These features make the LINT method especially suitable for high frequency applications emerging at upper microwave and millimeter-wave frequencies. A two-stage 12 frequency multiplier chain is employed for frequency translation, to evaluate the feasibility of the LINT architecture for generating 16-QAM modulation at 28 GHz. The effect of imperfections on modulator performance is also considered.

This paper presents the transmission performance of a class-IV partial-response signaling SSB system and proposes a method that can improve its power efficiency. A line code that has no dc component has been used in the SSB transmission of digital signals. The type of line code, such as a partial-response signaling, increases the modulation states, and as a result, decreases the power efficiency. To overcome this obstacle, a new demodulation method called "re-filtering and combining" is proposed on the assumption of orthogonal phase detection. The demodulated quadrature channel is re-filtered by a Hilbert filter and is combined with the in-phase channel. It is confirmed by computer simulations that the new demodulation method improves the BER performance and a 3 dB improvement of the power efficiency is obtained.

A new CMOS DC voltage doubler with nonoverlapping switching control is proposed, in order to eliminate the dynamic current loss during switching as well as the threshold voltage drop of the serial switches. The simulated results at 1.5 V show that the maximum power efficiency is improved with about 30%, whereas the efficiency in the low output current region is larger than 5 times compared to the conventional voltage doublers. This proposed CMOS DC voltage doubler can be used as a VPP generator of low voltage DRAM's.