There have been many studies on fault-tolerance for making highly reliable systems. As the demand for high-speed computers grows, the design of their clock systems becomes a major research subject not only in achieving high performance, but also in reducing assembly and maintenance costs. In this paper, two different kinds of highly reliable clock generators are proposed. Their hardware construction is very simple, because they have only several clock oscillators synchronized with each other using a coupling device. On the other hand, their usages are different. One is used as a crystal coupled clock generator to have a fault-tolerancy, and the other is used as a quick start clock generator for those systems which requires a rapid start necessarily. At first, clock synchronization of the multiple oscillators synchronized with each other using a coupling device, is discussed. This clock synchronization becomes the basic technique for the two clock generators which will be proposed in this paper. By connecting each oscillators using a coupling device, those oscillators easily synchronize with each other. Furthermore, by choosing coupling devices adequately, the proposed clock generator can have a fault tolerant property. Second, the crystal coupled fault-tolerant clock generator suitable for non stop operation even if one of the generators halts by some faults is proposed. To satisfy a fault tolerant property, the crystal resonator was found to have a good characteristic as a coupling device. This is because crystal shows a rapid transformation in the reactance value according to the small deviation of the oscillator's frequency. Finally, another clock generator with a quick start is also described. This quick start clock generator also consists of the coupled oscillator and it uses the same technique of the fault-tolerant clock generator. An oscillator having high Q ordinarily needs a longer set up time compared with those oscillators having a low Q. An oscillator coupled with a vibrating oscillator can start its oscillation quickly with a start of power supply.

This paper proposes a new fault tolerant intercommunication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed intercommunication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.

This paper presents a new information-theoretical evaluation method, for the resistance of cryptographic implementation against side-channel attacks. In conventional methods, the results of actual attacks have been often used empirically. However, these experimental methods have some problems. In the proposed method, a side-channel attack is regarded as a communication channel model. Then, a new evaluation index “the amount of leakage information” can be defined. The upper-bound of this index is estimated as the channel capacity. The proposed evaluation using this index can avoid the problems of conventional methods. Consequently, the proposed method provides some benefits: (1) It provides rationale for evaluation; (2) It enables execution of numerical evaluation and mutual evaluation among several kinds of countermeasures. This research achieves a unification of evaluation indexes for resistance against side-channel attack. This paper applies the proposed method to correlation power analysis against implementations of stream cipher Enocoro-128 v2. As a result, we confirmed its effectiveness.

Generally it is said that a fuzzy control system has fault tolerant properties, but it is not clearly studied. In this paper, first, the influence of faults in fuzzy control systems is examined. Errors given by fault simulation are not negligible. However, no fault detecting method is applied in the realized fuzzy control systems. Then a fault-checking method to detect faults is proposed in this paper.

Computer systems with GPUs are expected to become a strong methodology for high-speed encryption processing. Moreover, power consumption has remained a primary deterrent for such processing on devices of all sizes. However, GPU vendors are currently announcing their future roadmaps of GPU architecture development: Nvidia Corp. promotes the Kepler architecture and AMD Corp. emphasizes the GCN architecture. Therefore, we evaluated throughput and power efficiency of three 128-bit block ciphers on GPUs with recent Nvidia Kepler and AMD GCN architectures. From our experiments, whereas the throughput and per-watt throughput of AES-128 on Radeon HD 7970 (2048 cores) with GCN architecture are 205.0Gbps and 1.3Gbps/Watt respectively, those on Geforce GTX 680 (1536 cores) with Kepler architecture are, respectively, 63.9Gbps and 0.43Gbps/W; an approximately 3.2 times throughput difference occurs between AES-128 on the two GPUs. Next, we investigate the reasons for the throughput difference using our micro-benchmark suites. According to the results, we speculate that to ameliorate Kepler GPUs as co-processor of block ciphers, the arithmetic and logical instructions must be improved in terms of software and hardware.

Many-core computer systems with GPUs are coming into mainstream use from high-end computing, including supercomputers, to embedded processors. Consequently, the implementation of cryptographic methods on GPGPU is also becoming popular because of such systems' performance. However, many factors affect the performance of GPUs. To cope with this problem, we developed a new translator, HiCrypt, which can generate an optimized GPGPU program written in both of CUDA and OpenCL from a cipher program written in standard C language with directives. Users must annotate only variables and an encoding/decoding function, which are characteristics of cipher programs, with directives. To evaluate the translator, five representative cipher programs are translated into CUDA and OpenCL programs by the translator. Generated programs perform high throughput almost identical to hand optimized programs for all five cipher programs. HiCrypt will contribute to development and evaluate of new and various symmetric block ciphers using GPGPU.