IEICE TRANSACTIONS on Fundamentals
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
Summary :
In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.8 pp.1644-1652
- Publication Date
- 2007/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e90-a.8.1644
- Type of Manuscript
- PAPER
- Category
- Digital Signal Processing
Authors
Keyword
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Lan-Da VAN, Chin-Teng LIN, Yuan-Chu YU, "VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E90-A, no. 8, pp. 1644-1652, August 2007, doi: 10.1093/ietfec/e90-a.8.1644.
Abstract: In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.8.1644/_p
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@ARTICLE{e90-a_8_1644,
author={Lan-Da VAN, Chin-Teng LIN, Yuan-Chu YU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design},
year={2007},
volume={E90-A},
number={8},
pages={1644-1652},
abstract={In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.},
keywords={},
doi={10.1093/ietfec/e90-a.8.1644},
ISSN={1745-1337},
month={August},}
Copy
TY - JOUR
TI - VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1644
EP - 1652
AU - Lan-Da VAN
AU - Chin-Teng LIN
AU - Yuan-Chu YU
PY - 2007
DO - 10.1093/ietfec/e90-a.8.1644
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2007
AB - In this paper, we propose one low-computation cycle and power-efficient recursive discrete Fourier transform (DFT)/inverse DFT (IDFT) architecture adopting a hybrid of input strength reduction, the Chebyshev polynomial, and register-splitting schemes. Comparing with the existing recursive DFT/IDFT architectures, the proposed recursive architecture achieves a reduction in computation-cycle by half. Appling this novel low-computation cycle architecture, we could double the throughput rate and the channel density without increasing the operating frequency for the dual tone multi-frequency (DTMF) detector in the high channel density voice over packet (VoP) application. From the chip implementation results, the proposed architecture is capable of processing over 128 channels and each channel consumes 9.77 µW under 1.2 V@20 MHz in TSMC 0.13 1P8M CMOS process. The proposed VLSI implementation shows the power-efficient advantage by the low-computation cycle architecture.
ER -
English
