In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when VDD is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/ under the condition that the temperature range is from -40 to 125 and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.

A current mode buck/boost DC-DC converter with automatic mode transition is presented in this paper. At heavy load, a control scheme adaptively changes operation mode between peak and valley current modes to achieve high efficiency, small output voltage ripple, and fast transient response. The switching loss is reduced by operating in pure modes, and the conduction loss is reduced by decreasing the average inductor current in transition modes. At light load, the equivalent switching frequency is decreased to reduce the switching loss. An automatic mode transition between heavy load PWM mode and light load PFM mode is achieved by introducing an average load current sensing method. The converter has been implemented with a standard 0.5,$mu$m CMOS process. The output voltage ripple is less than 10,mV in all modes, and the peak efficiency is 95%.

By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18 µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5 V to 7 V and from 0.5 V to 5.6 V, respectively, using a 3 MHz clock.

A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.

The novel low-power and low-EMI-noise current-mode data transceiver described here, which has a multilevel current driver in the transmitter (TX) and a low-input impedance I-V converter in the receiver (RX). No-feedback clock recovery in the RX is achieved by using multi-levels of a driving current from TX to specify a single bit boundary. The I-V converter suppresses voltage swing in the transmission line and generates a multi-level voltage signal according to the level of the submilliampere driving current it receives. Measurement shows a small voltage swing ( 20 mV) with 150-µA and 450-µA drive currents at 625 Mbps. The simple clock-recovery system and low driving current allow the transceiver to operate with a single 1.5-V power supply and use only 3.5 mW at 625 Mbps.

This paper presents a new Fuzzy Logic Controller (FLC) having the ability to support rational-powered membership functions. These functions are extended forms of triangular/trapezoidal membership functions, and also those functions which are generated by applying linguistic hedges. A two-input, single-output, nine-rule Takagi-Sugeno-Kang (TSK) type FLC is designed in 0.35 µm standard CMOS technology. This controller can also be used as a standard (Mamdani) type FLC having singleton output membership functions, as well as a Linguistic Hedge FLC (LHFLC). Mixed analog/digital realization of the circuit makes the design programmable and extendable, while having relatively low power consumption. Current mode realization of the circuits leads to simple and intuitive configurations. For a particular set of programming parameters, simulation results of the controller using HSPICE simulator and level 49 parameters (BSIM3v3), show an average power consumption of 5 mW, and an RMS error of 1.32% compared to ideal results obtained from MATLAB software.

A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture using the Multiple-Valued Source-Coupled Logic (MVSCL) is proposed to implement special-purpose processors. An MV-FPVLSI consists of identical cells, which are connected to 8-neighborhood ones. To reduce the complexity of the interconnection block between two cells in an MV-FPVLSI, a bit-serial fine-grain pipeline architecture is introduced which allows single-wire data transmission and as a result, the data-transmission delay becomes very small in comparison with that of a conventional FPGA. To reduce the number of switches in the interconnection block further, a cell, using multiple-valued source-coupled logic circuits, is proposed, where the input currents can be linearly summed just by wiring without using any active devices. Not only the data, but also the control signal can be superposed by linear summation. As a result, no input switch is required which contributes to smaller data transmission delay. Moreover, an arbitrary 2-input logic function can be generated by linear summation of the input currents and threshold operations using these reconfigurable MVSCL circuits. As the MVSCL circuit has high driving capability in comparison with that of an equivalent CMOS circuit, high-speed logic operation is also possible while maintaining low power.

A readout circuit involving new two step current mode background suppression is studied for 2-dimensional long wavelength infrared focal plane arrays (LWIR FPA's). Buffered direct injection (BDI) and feedback amplifier structure are adopted for input circuit and background suppression circuit, respectively. The pixel circuit is simple and has very small skimming error less than 0.1%. Enough calibration range over 50% as well as long integration time over 1.75 ms can be obtained using this readout circuit.

New grounded capacitor realizations of second order and third order current mode Butterworth lowpass filters are given. The proposed circuits employ the current conveyor as the active element, and have the attractive property of using equal valued capacitors and equal valued resistors. PSpice simulation results are included.

We present a current mode cyclic analog-to-digital converter that is suitable for submicron LSI fabrication processes. Our converter is composed of sample-and-hold circuits with regulated cascode configuration which offers high output impedance and wide outoput range. The circuit requires small area since the architecture depends on neither precise analog transistors nor ratio-matched capacitors. We have designed and fabricated a test circuit that has an area of 0.014mm2 using a 0.8µm CMOS process. The circuit is examined to perform 8-bit resolution at a sampling rate of 40kHz and average power dissipation of 370µW at 4V supply voltage.

This paper presents an accurate and semi-physical MOSFET substrate current model suitable for analog circuit simulations. The proposed model is valid over a wide range of the electric field present in MOSFET devices and is continuous from cut off region to saturation region. The developed model was implemented into the circuit simulator, SPICE3. Benchmark of the developed model was achieved by making comparisons between the measured data and the simulated data for MOSFET devices, push-pull CMOS inverters, a regulated cascode CMOS operational amplifier. The experimental results showed that the developed model was more accurate and computationally efficient than the conventional models.

This paper presents 1V supply voltage Bi-CMOS current mode circuits. The circuits are consist of current mirrors, current comparators and current sources. The circuits have some advantages such as high accuracy, high speed, high density and low power supply. As an application of the circuits, an analog-to-digital converter (ADC) is given. The ADC operates with small chip area and low power dissipation. The performances of the proposed circuits were confirmed by using SPICE2 simulation.

A new current-mode dual-input configuration for the generation of a ratio (Y2/Y1) type network function using the second generation current conveyor (CC ) elements has been proposed. With nonideal CC s, a precise compensation of output current can be obtained simply by insertion of a grounded admittance (Yc). The design of precise insensitive current-mode integrator/differentiator type functional circuits follows directly if the Y1,2 admittances are suitably chosen as RC components.

The characteristics of voltage-resonant dc-dc converters have already been analyzed and described. However, in the conventional analysis, the inductance of the reactor is assumed to be infinity and the loss resistance of the power circuit is not taken into account. Also, in some cases, the averaging method is applied to analyze the resonant dc-dc converters as well as the pwm dc-dc converters. Consequently, the results from conventional analysis are not entirely in agreement with the experimental ones. This paper presents a general design-oriented analysis of the buck-boost type voltage-resonant dc-dc converter in the continuous and discontinuous modes of the reactor current. In this analysis, the loss resistance in each part of the power circuit, the inductance of the reactor, the effective value (not mean value) of the power loss, and the energy-balance among the input, output and internal-loss powers are taken into account. As a result, the behavior and characteristics of the buck-boost type voltage-resonant dc-dc converter are fully explained. It is also revealed that there is a useful mode in the discontinuous reactor current region, in which the output voltage can be regulated sufficiently for the load change from no load to full load and for the relatively large change of the input voltage, and then the change in the switching frequency can be kept relatively small.

This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.