This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 µm CMOS design rule.

It is well known that offset errors in the multipliers of neural LSIs can have fatal effects on performance. The aim of this study is to understand theoretically how offset errors affect performance of neural LSIs. We have used a single-layer perceptron as an example, and compare our theoretically derived results with computer simulations. We have found that offset errors in the multipliers for the forward process can be canceled out through learning, but those for the updating process cannot be. We have examined the asymptotic behavior of learning for the updating process and derived a mathematical expression for dL, the excess of the averaged loss function L. The derived expression gives us a basis for estimating robustness with respect to the offset errors. Our analysis indicates that dL can be expressed in the form of a quadratic form of offset errors and the inverse of the Hessian matrix of L. We have found that increasing the number of synapses degrades the performacne. We have also learned that enlarging the input signal level and reducing the signal level of the desired response can be effective techniques for reducing the effects of offset errors of the updating process.

A programmable clock generator, based on a phase-locked loop (PLL) circuit, has been developed with 0.5 µm CMOS triple-layer Al interconnection technology for use as an on-chip clock generator in a 300-MHz video signal processor. The PLL-based clock generator generates a clock signal whose frequency ranges from 50 to 350 MHz which is an integral multiple, from 2 to 16, of an external clock frequency. In order to achieve stable operation within this wide range, a voltage controlled oscillator (VCO) with selectable low VCO gain characteristics has been developed. Experimental results show that the clock generator generates a 297-MHz clock with a 27-MHz external clock, with jitter of 180 ps and power dissipation of 120 mW at 3.3-V power supply, and it can also oscillate up to 348 MHz with a 31.7-MHz external clock.

This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.