IEICE TRANSACTIONS on Fundamentals
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
Summary :
In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2463-2472
- Publication Date
- 2016/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.2463
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Tatsuya KAMAKARI
Kyoto University
Jun SHIOMI
Kyoto University
Tohru ISHIHARA
Kyoto University
Hidetoshi ONODERA
Kyoto University,JST
Keyword
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Tatsuya KAMAKARI, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, "Analytical Stability Modeling for CMOS Latches in Low Voltage Operation" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 12, pp. 2463-2472, December 2016, doi: 10.1587/transfun.E99.A.2463.
Abstract: In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2463/_p
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@ARTICLE{e99-a_12_2463,
author={Tatsuya KAMAKARI, Jun SHIOMI, Tohru ISHIHARA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Analytical Stability Modeling for CMOS Latches in Low Voltage Operation},
year={2016},
volume={E99-A},
number={12},
pages={2463-2472},
abstract={In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.},
keywords={},
doi={10.1587/transfun.E99.A.2463},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Analytical Stability Modeling for CMOS Latches in Low Voltage Operation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2463
EP - 2472
AU - Tatsuya KAMAKARI
AU - Jun SHIOMI
AU - Tohru ISHIHARA
AU - Hidetoshi ONODERA
PY - 2016
DO - 10.1587/transfun.E99.A.2463
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - In synchronous LSI circuits, memory subsystems such as Flip-Flops and SRAMs are essential components and latches are the base elements of the common memory logics. In this paper, a stability analysis method for latches operating in a low voltage region is proposed. The butterfly curve of latches is a key for analyzing a retention failure of latches. This paper discusses a modeling method for retention stability and derives an analytical stability model for latches. The minimum supply voltage where the latches can operate with a certain yield can be accurately derived by a simple calculation using the proposed model. Monte-Carlo simulation targeting 65nm and 28nm process technology models demonstrates the accuracy and the validity of the proposed method. Measurement results obtained by a test chip fabricated in a 65nm process technology also demonstrate the validity. Based on the model, this paper shows some strategies for variation tolerant design of latches.
ER -
English
