This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0 V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7 V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400 mV.

Multi-Gate device technology is the promising candidate for the enhancement of device characteristics of the scaled MOSFETs. Moreover, independent-double-gate devices have been proposed to achieve flexible Vth adjustment. It is revealed that the SRAM noise margins have been increased by introducing the independent-double-gate FinFET.

Aiming at drastically reducing standby leakage current, an SRAM using Four-Terminal- (4T-) FinFETs, named Flex-Vth SRAM, with a dynamic row-by-row threshold voltage control (RRTC) was developed. The Flex-Vth SRAM realizes an extremely low standby-leakage current thanks to the flexible threshold-voltage (Vth) controllability of the 4T-FinFETs, while its access speed and static noise margin (SNM) are maintained. A TCAD-based Monte Carlo simulation indicates that even when the process-induced random variation in the device performance is taken into account, the Flex-Vth SRAM reduces the leakage current to 1/100 of that of a standard SRAM in a 256256 array, where 20-nm-gate-length technologies with the same on-current are assumed.

This paper presents a precise characterization of high-frequency characteristics of intrinsic channel of FinFET. For the de-embedding of the parasitics attached to the source, drain and gate terminals, it proposes special calibration patterns which can place the reference surface just beside the intrinsic part of the FinFET. It compares the measured S parameter data up to 40 GHz with the device simulation and shows good matching. The experimental data of the through pattern also confirms the accuracy of the de-embedded parasitics and extracted intrinsic part of FinFET.

We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.