In this paper, we propose a distributed subgradient-based method over quantized and event-triggered communication networks for constrained convex optimization. In the proposed method, each agent sends the quantized state to the neighbor agents only at its trigger times through the dynamic encoding and decoding scheme. After the quantized and event-triggered information exchanges, each agent locally updates its state by a consensus-based subgradient algorithm. We show a sufficient condition for convergence under summability conditions of a diminishing step-size.

This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.

The packet classification problem to determine the behavior of incoming packets at the network devices. The processing latency of packet classification by linear search is proportional to the number of classification rules. To limit the latency caused by classification to a certain level, we should develop a classification algorithm that classifies packets in a time independent of the number of classification rules. Arbitrary (including noncontiguous) bitmask rules are efficiently expressive for controlling higher layer communication, achiving access control lists, Quality of Service and so on. In this paper, we propose a classification algorithm based on run-based trie [1] according to arbitrary bitmask rules. The space complexity of proposed algorithm is in linear in the size of a rule list. The time complexity except for construction of that can be regarded as constant which is independent the number of rules. Experimental results using a packet classification algorithm benchmark [2] show that our method classifies packets in constant time independent of the number of rules.

Recently, cars are equipped with a lot of sensors for safety driving. We have been trying to store the driving-scene video with such sensor data and to detect the change of scenery of streets. Detection results can be used for building historical database of town scenery, automatic landmark updating of maps, and so forth. In order to compare images to detect changes, image retrieval taken at nearly identical locations is required as the first step. Since Global Positioning System (GPS) data essentially contain some noises, we cannot rely only on GPS data for our image retrieval. Therefore, we have developed an image retrieval algorithm employing edge-histogram-based image features in conjunction with hierarchical search. By using edge histograms projected onto the vertical and horizontal axes, the retrieval has been made robust to image variation due to weather change, clouds, obstacles, and so on. In addition, matching cost has been made small by limiting the matching candidates employing the hierarchical search. Experimental results have demonstrated that the mean retrieval accuracy has been improved from 65% to 76% for the front-view images and from 34% to 53% for the side-view images.

Generating conditions of the optical feedback noise in self-pulsing lasers were experimentally examined. The noise charcteristics were determined by changing the operating power, the feedback distance and the feedback ratio for several types of self-pulsing lasers. The idea of the effective modulation index was introduced to evaluate the generating conditions in an uniform manner based on the mode competition theory. Validity of the idea was experimentally confirmed for generation of noise.

Refinement-based formal specification is a promising approach to the increasing complexity of software systems, as demonstrated in the formal method Event-B. It allows stepwise modeling and verifying of complex systems with multiple steps at different abstraction levels. However, making changes is more difficult, as caution is necessary to avoid breaking the consistency between the steps. Judging whether a change is valid or not is a non-trivial task, as the logical dependency relationships between the modeling elements (predicates) are implicit and complex. In this paper, we propose a method for analyzing the impact of the changes of Event-B. By attaching labels to modeling elements (predicates), the method helps engineers understand how a model is structured and what needs to be modified to accomplish a change.

In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.

RF integration, until recently the integration of active devices in conventional architectures suitable for discrete-component circuits, is now turning into full-integration based on new architectures developed specifically for an LSI technology. This paper reviews some of the key existing and emerging circuit techniques and discusses the serious problem of crosstalk. In order to develop miniature and low power RF transceivers, direct-conversion and monolithic VCO's will be further studied. Silicon bipolar technology will still be playing major role beyond the year 2,000, and CMOS will also be used in certain applications.

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0 V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7 V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400 mV.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.

As a variety of digital services are provided through networks, more and more efforts are made to ensure dependability of software behavior implementing services. Formal methods and tools have been considered as promising means to support dependability in complex software systems during the development. On the other hand, there have been serious doubts on practical applicability of formal methods. This paper overviews the present state of formal methods and discusses their applicability, especially focusing on two representative methods (SPIN and B Method) and their recent industrial applications. This paper also discusses applications of formal methods to dependable networked software.

This paper studies nonlinear dynamics of a simplified model of multiple-input parallel buck converters. The dynamic winner-take-all switching is used to achieve N-phase synchronization automatically, however, as parameters vary, the synchronization bifurcates to a variety of periodic/chaotic phenomena. In order to analyze system dynamics we adopt a simple piecewise constant modeling, extract essential parameters in a dimensionless circuit equation and derive a hybrid return map. We then investigate typical bifurcation phenomena relating to N-phase synchronization, hyperchaos, complicated superstable behavior and so on. Ripple characteristics are also investigated.

A low power consumption 16-bit fixed point Digital Signal Processor (DSP) has been developed to realize a half-rate CODEC for the Personal Digital Cellular (PDC) system. Dual datapath architecture has been employed to execute multiply-accumulate (MAC) operations with a high degree of efficiency. With this architecture. 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (PSI-CELP) program are executed in parallel, so that total instruction cycles are reduced by 23.1%. The area overhead for the dual datapath architecture is only 3.0% of the total area. Furthermore, in order to reduce power consumption, circuit design techniques are also extensively applied to RAMs. ROMs, and clock circuits, which consume the great majority of power. By reducing the number of precharging bit lines, a power reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achieved in the DSP that performs the PSI-CELP algorithm. The DSP is fabricated in 0.5 µm single-poly, double-metal CMOS technology. The PSI-CELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz instruction frequency and 1.6 V supply voltage. resulting in a low-power consumption of 28 mW.

In orthogonal frequency division multiplexing (OFDM) system, a guard interval (GI) is used to remove the inter-symbol interference (ISI) due to a multipath channel. It is difficult to set an optimal GI length in the environment whose multipath varies. In this paper, we propose a variable guard interval based on the estimated maximum delay of a multipath channel. The maximum delay is estimated from a channel impulse response (CIR), which is estimated by a preamble symbol. However, since the estimated CIR includes the noise, it is difficult to decide the optimal GI. In order to solve the problem, we introduce the method which selects the path whose signal to noise ratio is high. Additionally, the information of the optimal GI length is required to be transmitted from a receiver to a transmitter. In this paper, we use an acknowledgment (ACK) frame for the feedback of the GI information.

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [µm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

Room temperature cw operation of transverse mode stabilized 680-nm InGaAIP laser diodes have been achieved for the first time. A self-aligned structure was fabricated by two-step metalorganic chemical vapor deposition, which included the selective growth technique.

A new switches-capacitor immittance converter (SCIC) circuit based on the bilinear transformation is propose. The inductive (n+1)-terminal network is realized using in SCIC's and one capacitive (n+1)-terminal network. The SCIC consists of only one buffer, one op amp and three capacitors.

Mixed-signal LSIs promise to permit increased levels of integration, not only in voiceband but also in multi-GHz-band applications such as wireless communications and optical data links. This paper reviews the evolution of mixed-signal communications LSIs and discusses some of their design problems, including device noise and crosstalk noise. In the low-power and low-voltage designs emerging as new disciplines, the target supply voltage for voiceband LSIs is around 1 V, and even GHz-band circuits are approaching 2 V. MOS devices are expected to play an important role even in the frequency range over 100 MHz, in the area of wireless or optical communications circuits.

How to minimize the number of mirroring resources under a QoS constraint (resource minimization problem) is an important issue in content delivery networks. This paper proposes a novel approach that takes advantage of the parallelism of dynamically reconfigurable processors (DRPs) to solve the resource minimization problem, which is NP-hard. Our proposal obtains the optimal solution by running an exhaustive search algorithm suitable for DRP. Greedy algorithms, which have been widely studied for tackling the resource minimization problem, cannot always obtain the optimal solution. The proposed method is implemented on an actual DRP and in experiments reduces the execution time by a factor of 40 compared to the conventional exhaustive search algorithm on a Pentium 4 (2.8 GHz).

This paper presents a precise characterization of high-frequency characteristics of intrinsic channel of FinFET. For the de-embedding of the parasitics attached to the source, drain and gate terminals, it proposes special calibration patterns which can place the reference surface just beside the intrinsic part of the FinFET. It compares the measured S parameter data up to 40 GHz with the device simulation and shows good matching. The experimental data of the through pattern also confirms the accuracy of the de-embedded parasitics and extracted intrinsic part of FinFET.