A Mixed-Signal Digital Signal Processor for Single-Chip Speech Codec

Takeshi TOKUDA; Tohru KENGAKU; Eiichi TERAOKA; Ikuo YASUI; Taketora SHIRAISHI; Hisako SAWAI; Koji KAWAMOTO; Kazuyuki ISHIKAWA; Toshiki FUZIYAMA; Narumi SAKASHITA; Hiroichi ISHIDA; Shinya TAKAHASHI; Takahiko IIDA

A Mixed-Signal Digital Signal Processor for Single-Chip Speech Codec

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This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E75-C No.10 pp.1241-1249

Publication Date: 1992/10/25

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Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors)

Category: Application Specific Processors

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Takeshi TOKUDA, Tohru KENGAKU, Eiichi TERAOKA, Ikuo YASUI, Taketora SHIRAISHI, Hisako SAWAI, Koji KAWAMOTO, Kazuyuki ISHIKAWA, Toshiki FUZIYAMA, Narumi SAKASHITA, Hiroichi ISHIDA, Shinya TAKAHASHI, Takahiko IIDA, "A Mixed-Signal Digital Signal Processor for Single-Chip Speech Codec" in IEICE TRANSACTIONS on Electronics, vol. E75-C, no. 10, pp. 1241-1249, October 1992, doi: .
Abstract: This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_10_1241/_p

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@ARTICLE{e75-c_10_1241,
author={Takeshi TOKUDA, Tohru KENGAKU, Eiichi TERAOKA, Ikuo YASUI, Taketora SHIRAISHI, Hisako SAWAI, Koji KAWAMOTO, Kazuyuki ISHIKAWA, Toshiki FUZIYAMA, Narumi SAKASHITA, Hiroichi ISHIDA, Shinya TAKAHASHI, Takahiko IIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Mixed-Signal Digital Signal Processor for Single-Chip Speech Codec},
year={1992},
volume={E75-C},
number={10},
pages={1241-1249},
abstract={This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - A Mixed-Signal Digital Signal Processor for Single-Chip Speech Codec
T2 - IEICE TRANSACTIONS on Electronics
SP - 1241
EP - 1249
AU - Takeshi TOKUDA
AU - Tohru KENGAKU
AU - Eiichi TERAOKA
AU - Ikuo YASUI
AU - Taketora SHIRAISHI
AU - Hisako SAWAI
AU - Koji KAWAMOTO
AU - Kazuyuki ISHIKAWA
AU - Toshiki FUZIYAMA
AU - Narumi SAKASHITA
AU - Hiroichi ISHIDA
AU - Shinya TAKAHASHI
AU - Takahiko IIDA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 1992
AB - This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.
ER -