A low power consumption 16-bit fixed point Digital Signal Processor (DSP) has been developed to realize a half-rate CODEC for the Personal Digital Cellular (PDC) system. Dual datapath architecture has been employed to execute multiply-accumulate (MAC) operations with a high degree of efficiency. With this architecture. 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (PSI-CELP) program are executed in parallel, so that total instruction cycles are reduced by 23.1%. The area overhead for the dual datapath architecture is only 3.0% of the total area. Furthermore, in order to reduce power consumption, circuit design techniques are also extensively applied to RAMs. ROMs, and clock circuits, which consume the great majority of power. By reducing the number of precharging bit lines, a power reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achieved in the DSP that performs the PSI-CELP algorithm. The DSP is fabricated in 0.5 µm single-poly, double-metal CMOS technology. The PSI-CELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz instruction frequency and 1.6 V supply voltage. resulting in a low-power consumption of 28 mW.

This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.