A built-in self-test (BIST) based on a signature-analysis (one of the data compression techniques) has been implemented in a 24 bit floating point digital signal processor (DSP). By using only a single pair of linear feedback shift registers (LFSR's) and 253 words of instruction of the DSP, 95% of the functional blocks are self-tested. The number of test patterns is 35 million. It takes only 2.6 seconds for the test at fc26.7 MHz. The overhead of the BIST hardware is about 2.0% of the die size. By comparing the pass rate in a conventional function test to the BIST, nearly the same fault coverage is obtained. This result shows that the BIST is effective for VLSI processors, such as DSPs. By improving this method, manufacturing go/no-go tests without expensive test equipment will be possible.

This paper describes a high-performance, low-power, mixed-signal Digital Signal Processor (DSP) and its application to a single-chip Vector Sum Excited Linear Prediction (VSELP) speech codec. The DSP consists of a 25MIPS, 24bit floating point core-DSP; 13bit oversampling ADC/DAC; 6 KW data ROM; and 3.5 KW data RAM. The total transistor counts of the DSP is 1.3 million and its chip size is 11.0 mm15.8 mm. Unique design techniques are used to reduce the power dissipation, such as the programmable machine cycle time control and the clock supply control scheme in the core-DSP, the address detection for on-chip data ROM/RAM, and the shared-hardware design for digital filters of ADC and DAC. As an application of the DSP, the VSELP speech codec, which is the standard speech codec for the North American and Japanese digital cellular telephone system, has been implemented in a single-chip. Owing ti the salient architecture design and the program optimization techniques, sufficient quality was obtained in the codec at performance of 16.4 MIPS with low-power dissipation of 490 mW.

A fuzzy inference processor which performs fuzzy inference with 12-bit resolution input at 200 kFLIPS (Fuzzy Logical Inference Per Second) has been developed. To keep the cost performance, not parallel processing hardware but processor type hardware is employed. Dedicated membership function generators, rule instructions and modified add/divide algorithm are adopted to attain the performance. The membership function generators calculate a membership function value in less than a half clock cycle. Rule instructions calculate the grade of a rule by one instruction. Antecedent processing and consequent processing are pipelined by the modified add/divide algorithm. As a result, total inference time is significantly reduced. For example, in the case of typical inference (about 20 rules with 2 to 4 inputs and 1 output), the total inference needs approximately 100 clock cycles. Furthermore by adding a mechanism to calculate the variance and maximum grade of the final membership function, it is enabled to evaluate the inference reliability. The chip, fabricated by 1 µm CMOS technology, contains 86k transistors in a 7.56.7 mm die size. The chip operates at more than 20 MHz clock frequency at 5 V.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.