Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.

This paper presents the architecture of a newly-developed dual-issue RISC processor, D10V, that achieves both high throughput signal processing capability and maintains flexibility for general purpose applications. The RISC processor uses a 2-way VLIW architecture with a 32-bit wide instruction word. Two sub-instructions in a VLIW instruction are executed in two execution units in parallel. It also has several enhancements for signal processing. The processor includes pipelined multiply-and-accumulate instructions allowing a new multiply operation to be initiated every clock cycle and block repeat instructions for zero delay penalty loops. Single-cycle data moves of double-word data elements with modulo addressing are provided to deliver required memory bandwidth for signal processing applications. As a result, the D10V achieves high signal processing capability as 1 clock cycle per tap for FIR filtering. Also, several DSP benchmarks illustrate that the D10V competes favorably and in some instances outperforms conventional 16-bit DSPs. For master controlling application, the processor provides memory operations for signed/unsigned byte and bit wise operations. It shows 49 Dhrystone MIPS at 52 MHz, for general purpose applications.