IEICE TRANSACTIONS on Fundamentals
A Low Voltage Stochastic Flash ADC without Comparator
Summary :
A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.7 pp.886-893
- Publication Date
- 2019/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E102.A.886
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Xuncheng ZOU
The University of Kitakyushu
Shigetoshi NAKATAKE
The University of Kitakyushu
Keyword
Latest Issue
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Xuncheng ZOU, Shigetoshi NAKATAKE, "A Low Voltage Stochastic Flash ADC without Comparator" in IEICE TRANSACTIONS on Fundamentals,
vol. E102-A, no. 7, pp. 886-893, July 2019, doi: 10.1587/transfun.E102.A.886.
Abstract: A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E102.A.886/_p
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@ARTICLE{e102-a_7_886,
author={Xuncheng ZOU, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Voltage Stochastic Flash ADC without Comparator},
year={2019},
volume={E102-A},
number={7},
pages={886-893},
abstract={A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.},
keywords={},
doi={10.1587/transfun.E102.A.886},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A Low Voltage Stochastic Flash ADC without Comparator
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 886
EP - 893
AU - Xuncheng ZOU
AU - Shigetoshi NAKATAKE
PY - 2019
DO - 10.1587/transfun.E102.A.886
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E102-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2019
AB - A low voltage stochastic flash ADC (analog-to-digital converter) is presented, with an inverter-based comparative unit which is used to replace comparator for comparison. Aiming at the low voltage and low power consumption, a key of our design is in the simplicity of the structure. The inverter-based comparative unit replacing a comparator enables us to decrease the number of transistors for area saving and power reduction. We insert the inverter-chain in front of the comparative unit for the signal stability and discuss an appropriate circuit structure for the resolution by analyzing three different ones. Finally, we design the whole stochastic flash ADC for verifying our idea, where the supply voltage can go down to 0.6V on the 65nm CMOS process, and through post-layout simulation result, we can observe its advantage visually in voltage, area and power consumption.
ER -
English
