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[Author] Takaaki TSUJI(2hit)

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  • Design of a Low-Voltage, Low-Power, High-Frequency CMOS Current-Mode VCO Circuit by Using 0.6µm MOS Devices

    Yasuhiro SUGIMOTO  Takeshi UENO  Takaaki TSUJI  

     
    PAPER

      Vol:
    E80-A No:2
      Page(s):
    304-312

    We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

  • Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit

    Yasuhiro SUGIMOTO  Takaaki TSUJI  

     
    LETTER

      Vol:
    E79-A No:5
      Page(s):
    630-633

    This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.