Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit

Yasuhiro SUGIMOTO; Takaaki TSUJI

Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit

Yasuhiro SUGIMOTO, Takaaki TSUJI

Full Text Views

0

Cite this

Summary :

This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.5 pp.630-633

Publication Date: 1996/05/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1995 Society Conference of IEICE)

Category

Cite this

Copy

Yasuhiro SUGIMOTO, Takaaki TSUJI, "Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 5, pp. 630-633, May 1996, doi: .
Abstract: This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_5_630/_p

Copy

@ARTICLE{e79-a_5_630,
author={Yasuhiro SUGIMOTO, Takaaki TSUJI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit},
year={1996},
volume={E79-A},
number={5},
pages={630-633},
abstract={This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.},
keywords={},
doi={},
ISSN={},
month={May},}

Copy

TY - JOUR
TI - Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 630
EP - 633
AU - Yasuhiro SUGIMOTO
AU - Takaaki TSUJI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 1996
AB - This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.
ER -