This paper examines the feasibility of a high frequency (moro than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed corrent-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 µm device paramenters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.